[1/4] dt-bindings: iio: frequency: add adf4377 doc
Commit Message
Add device tree bindings for the ADF4377 driver.
Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
.../bindings/iio/frequency/adi,adf4377.yaml | 78 +++++++++++++++++++
1 file changed, 78 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/frequency/adi,adf4377.yaml
Comments
On 04/11/2022 05:27, Antoniu Miclaus wrote:
> Add device tree bindings for the ADF4377 driver.
Subject: drop "doc"
>
> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> ---
> .../bindings/iio/frequency/adi,adf4377.yaml | 78 +++++++++++++++++++
> 1 file changed, 78 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/frequency/adi,adf4377.yaml
>
> diff --git a/Documentation/devicetree/bindings/iio/frequency/adi,adf4377.yaml b/Documentation/devicetree/bindings/iio/frequency/adi,adf4377.yaml
> new file mode 100644
> index 000000000000..3f5c83e03bb9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/frequency/adi,adf4377.yaml
> @@ -0,0 +1,78 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/frequency/adi,adf4377.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ADF4377 Microwave Wideband Synthesizer with Integrated VCO
> +
> +maintainers:
> + - Antoniu Miclaus <antoniu.miclaus@analog.com>
> + - Dragos Bogdan <dragos.bogdan@analog.com>
> +
> +description: |
> + The ADF4377 is a high performance, ultralow jitter, dual output integer-N
> + phased locked loop (PLL) with integrated voltage controlled oscillator (VCO)
> + ideally suited for data converter and mixed signal front end (MxFE) clock
> + applications.
> +
> + https://www.analog.com/en/products/adf4377.html
> +
> +properties:
> + compatible:
> + enum:
> + - adi,adf4377
> + - adi,adf4378
> +
> + reg:
> + maxItems: 1
> +
> + spi-max-frequency:
> + maximum: 10000000
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + description:
> + External clock that provides reference input frequency.
> + items:
> + - const: ref_in
> +
> + ce-en-gpios:
chip-enable-gpios
> + description:
> + Gpio that controls the Chip Enable Pin.
s/Gpio/GPIO/
(other places as well)
> + maxItems: 1
> +
> + enclk1-gpios:
clk1-enable-gpios
> + description:
> + Gpio that controls the Enable Clock 1 Output Buffer Pin.
> + maxItems: 1
> +
> + enclk2-gpios:
clk2-enable-gpios
> + description:
> + Gpio that controls the Enable Clock 2 Output Buffer Pin.
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> +
allOf with reference to spi-peripheral-props.yaml
> +additionalProperties: false
> +
> +examples:
> + - |
> + spi {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + frequency@0 {
> + compatible = "adi,adf4377";
> + reg = <0>;
> + spi-max-frequency = <10000000>;
> + clocks = <&adf4377_ref_in>;
> + clock-names = "ref_in";
> + };
> + };
> +...
Best regards,
Krzysztof
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - clock-names
> > +
>
> allOf with reference to spi-peripheral-props.yaml
>
> > +additionalProperties: false
switch to unevaluatedProperties: false
as well when you do the spi-peripheral-props.yaml addition.
Easy to forget.
Jonathan
> > +
> > +examples:
> > + - |
> > + spi {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + frequency@0 {
> > + compatible = "adi,adf4377";
> > + reg = <0>;
> > + spi-max-frequency = <10000000>;
> > + clocks = <&adf4377_ref_in>;
> > + clock-names = "ref_in";
> > + };
> > + };
> > +...
>
> Best regards,
> Krzysztof
>
new file mode 100644
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/frequency/adi,adf4377.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ADF4377 Microwave Wideband Synthesizer with Integrated VCO
+
+maintainers:
+ - Antoniu Miclaus <antoniu.miclaus@analog.com>
+ - Dragos Bogdan <dragos.bogdan@analog.com>
+
+description: |
+ The ADF4377 is a high performance, ultralow jitter, dual output integer-N
+ phased locked loop (PLL) with integrated voltage controlled oscillator (VCO)
+ ideally suited for data converter and mixed signal front end (MxFE) clock
+ applications.
+
+ https://www.analog.com/en/products/adf4377.html
+
+properties:
+ compatible:
+ enum:
+ - adi,adf4377
+ - adi,adf4378
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 10000000
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ description:
+ External clock that provides reference input frequency.
+ items:
+ - const: ref_in
+
+ ce-en-gpios:
+ description:
+ Gpio that controls the Chip Enable Pin.
+ maxItems: 1
+
+ enclk1-gpios:
+ description:
+ Gpio that controls the Enable Clock 1 Output Buffer Pin.
+ maxItems: 1
+
+ enclk2-gpios:
+ description:
+ Gpio that controls the Enable Clock 2 Output Buffer Pin.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ frequency@0 {
+ compatible = "adi,adf4377";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ clocks = <&adf4377_ref_in>;
+ clock-names = "ref_in";
+ };
+ };
+...