soc: qcom: geni-se: Do not bother about enable/disable of interrupts in secondary sequencer for non-uart modes
Message ID | 1685729609-26871-1-git-send-email-quic_vnivarth@quicinc.com |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1216319vqr; Fri, 2 Jun 2023 11:19:39 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ558BdzRJrH5kZPFXzXXYIE4km2gjQ88Q7xSh4FatOtqzIF22IHx9KXZXKFJGUO72S2Nkmt X-Received: by 2002:a17:902:f7cc:b0:1af:beae:c0b with SMTP id h12-20020a170902f7cc00b001afbeae0c0bmr662727plw.22.1685729979264; Fri, 02 Jun 2023 11:19:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685729979; cv=none; d=google.com; s=arc-20160816; b=VLXfcBhFS+qvKrKLFyESLNpna1GN4kw5stFlWTB0DNCGXJtfP3uhJr/kFzDndyMA/D 2DCf9k70Lqdqx9YO7+8ne4leo8BjeWIlPYNyQ+aEyYeMbONMpIcGqdkAtALAgdpsLC4n tcKweK3Co+1dq8GxknXn/Qh3WjxA1ZZcaesXqXbl/Z2ip1XitXelepLVGrplZA8uKVBF OCm+Q8ZZcAvQsw88iuADIuMpDeVC5qaWXtcrrbTMlUFSjW/QKpFHSyCO7luPusF7KMwo T2s4e61cXg8RnhNc6EcWinraP6SAJRQrnUit0sNiavB8dQrHrjOGjYsIK3NIDTuLvGqQ pzwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:message-id:date:subject:cc:to:from :dkim-signature; bh=UE2Rx1irt7g58Lw65av8HRXfkxaMlYFe/H8y1ZB0miQ=; b=WawL1ArNDm5WCu9zG7bL0JsKrgmSqLciArgLu7s/zhKq1+OMuDHgT3YHfNK9m7WXYG jCYi+RD7XrP9Vv483FS6wTotVypp8lC4rzgdZx89JqMVygaTlW+kF3JmqYVWkqA6h0rG GmzIps6q2Qa2U7Yca0uCw8B8PqzVZ3m1ZTai/XbwuhFcnlwX+RH0HaOQlTiJs7d/N58H 7+PrbYFfFVlwBT9Jk/RXIe2In7CmvQ+Cq0Rqnzt/dPUpzPeXl9fuQ5FHZQxXU2Fwg9WJ MfSAHWSUOeI3Oa7ggpAjivNPEstMu8ZeQT3G6TgnkyKEmgdTKRkSkPpwS5mnPf412nfQ el6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=EEBowLTe; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id c11-20020a170902d48b00b001a6b5a7db52si1257516plg.596.2023.06.02.11.19.25; Fri, 02 Jun 2023 11:19:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=EEBowLTe; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235481AbjFBSNt (ORCPT <rfc822;limurcpp@gmail.com> + 99 others); Fri, 2 Jun 2023 14:13:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232628AbjFBSNr (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Fri, 2 Jun 2023 14:13:47 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB6D9123; Fri, 2 Jun 2023 11:13:46 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 352Dg9Rw029446; Fri, 2 Jun 2023 18:13:42 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id; s=qcppdkim1; bh=UE2Rx1irt7g58Lw65av8HRXfkxaMlYFe/H8y1ZB0miQ=; b=EEBowLTeDOi23kCV6ogPf76qKhh/f3fkLD2wj173SgWhGMNWYsefgY52RT9TaxQtSdH4 b+UJ2Yb3S9XkGGNM9w2po2mNGAyTLZ5xYwF5Txm4gqo/QWDKIlUeRSYxTpHrzNbQYqtv Xgpk/1lV1lempWCYVdzCwtpDfMuc/ciDWXt4LLJ12YkSnJOyQgfungYYVCijsy6eN8pT DRW290KeGKP0cABQzjUKBb5UM2+b3/TA34oLArekg9FncytNH4TK0I+raLEQ5sMnG5dP j6vksAckQH1sKBKR8zs1SJ3yp9YF4L5l8vHujxDPb0qLiCJCLQbjn1MIFqgYiCaUs1in jw== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qybqeheke-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 02 Jun 2023 18:13:41 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 352IACvG008476; Fri, 2 Jun 2023 18:13:37 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3quaxknu2p-1; Fri, 02 Jun 2023 18:13:37 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 352IDbxj011176; Fri, 2 Jun 2023 18:13:37 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-vnivarth-hyd.qualcomm.com [10.213.111.166]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 352IDbIc011175; Fri, 02 Jun 2023 18:13:37 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3994820) id A82284B62; Fri, 2 Jun 2023 23:43:36 +0530 (+0530) From: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: quic_msavaliy@quicinc.com, dianders@chromium.org, mka@chromium.org, swboyd@chromium.org, quic_vtanuku@quicinc.com, Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> Subject: [PATCH] soc: qcom: geni-se: Do not bother about enable/disable of interrupts in secondary sequencer for non-uart modes Date: Fri, 2 Jun 2023 23:43:29 +0530 Message-Id: <1685729609-26871-1-git-send-email-quic_vnivarth@quicinc.com> X-Mailer: git-send-email 2.7.4 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: xILEjNoPTC-f7nFT4HVfjCt609Rl4del X-Proofpoint-GUID: xILEjNoPTC-f7nFT4HVfjCt609Rl4del X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-02_13,2023-06-02_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=410 mlxscore=0 adultscore=0 spamscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 impostorscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2306020139 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767615998342620367?= X-GMAIL-MSGID: =?utf-8?q?1767615998342620367?= |
Series |
soc: qcom: geni-se: Do not bother about enable/disable of interrupts in secondary sequencer for non-uart modes
|
|
Commit Message
Vijaya Krishna Nivarthi
June 2, 2023, 6:13 p.m. UTC
The select_fifo/dma_mode() functions in geni driver enable/disable
interrupts (secondary included) conditionally for non-uart modes, while
uart is supposed to manage this internally.
However, only uart uses secondary IRQs while spi, i2c do not care about
these at all making their enablement (or disablement) totally unnecessary
for these protos.
Drop enabling/disabling secondary IRQs for non-uart modes.
This doesn't solve any observed problem but only gets rid of code pieces
that are not required.
Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>
---
drivers/soc/qcom/qcom-geni-se.c | 24 ++++--------------------
1 file changed, 4 insertions(+), 20 deletions(-)
Comments
Hi, On Fri, Jun 2, 2023 at 11:13 AM Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> wrote: > > The select_fifo/dma_mode() functions in geni driver enable/disable > interrupts (secondary included) conditionally for non-uart modes, while > uart is supposed to manage this internally. > However, only uart uses secondary IRQs while spi, i2c do not care about > these at all making their enablement (or disablement) totally unnecessary > for these protos. > > Drop enabling/disabling secondary IRQs for non-uart modes. > This doesn't solve any observed problem but only gets rid of code pieces > that are not required. > > Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> > --- > drivers/soc/qcom/qcom-geni-se.c | 24 ++++-------------------- > 1 file changed, 4 insertions(+), 20 deletions(-) This seems like a nice cleanup to me. It's still odd that the general code has a special case for UART, but I guess the alternative is to duplicate the exact same logic for both the i2c and SPI drivers. I won't insist on that, though I wouldn't be opposed to it either. I guess one comment, though: should we also remove the code that messes with "SE_GENI_S_IRQ_EN" in geni_se_select_gpi_mode()? -Doug
Hi, Thank you very much for the review... On 6/7/2023 9:41 PM, Doug Anderson wrote: > Hi, > > On Fri, Jun 2, 2023 at 11:13 AM Vijaya Krishna Nivarthi > <quic_vnivarth@quicinc.com> wrote: >> The select_fifo/dma_mode() functions in geni driver enable/disable >> interrupts (secondary included) conditionally for non-uart modes, while >> uart is supposed to manage this internally. >> However, only uart uses secondary IRQs while spi, i2c do not care about >> these at all making their enablement (or disablement) totally unnecessary >> for these protos. >> >> Drop enabling/disabling secondary IRQs for non-uart modes. >> This doesn't solve any observed problem but only gets rid of code pieces >> that are not required. >> >> Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> >> --- >> drivers/soc/qcom/qcom-geni-se.c | 24 ++++-------------------- >> 1 file changed, 4 insertions(+), 20 deletions(-) > This seems like a nice cleanup to me. It's still odd that the general > code has a special case for UART, but I guess the alternative is to > duplicate the exact same logic for both the i2c and SPI drivers. I > won't insist on that, though I wouldn't be opposed to it either. > > I guess one comment, though: should we also remove the code that > messes with "SE_GENI_S_IRQ_EN" in geni_se_select_gpi_mode()? Right now we have gpi-dma mode support for i2c and spi but not for uart. Even when gpi-dma support is added, uart driver's interrupt handler would not be invoked so I believe it would be safe to drop that code from geni_se_select_gpi_mode() too. I will post v2 dropping same after some more lookup. -Vijay/ > > -Doug
Hi, On 6/12/2023 7:09 PM, Vijaya Krishna Nivarthi wrote: > Hi, > > Thank you very much for the review... > > > On 6/7/2023 9:41 PM, Doug Anderson wrote: >> Hi, >> >> On Fri, Jun 2, 2023 at 11:13 AM Vijaya Krishna Nivarthi >> <quic_vnivarth@quicinc.com> wrote: >>> The select_fifo/dma_mode() functions in geni driver enable/disable >>> interrupts (secondary included) conditionally for non-uart modes, while >>> uart is supposed to manage this internally. >>> However, only uart uses secondary IRQs while spi, i2c do not care about >>> these at all making their enablement (or disablement) totally >>> unnecessary >>> for these protos. >>> >>> Drop enabling/disabling secondary IRQs for non-uart modes. >>> This doesn't solve any observed problem but only gets rid of code >>> pieces >>> that are not required. >>> >>> Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> >>> --- >>> drivers/soc/qcom/qcom-geni-se.c | 24 ++++-------------------- >>> 1 file changed, 4 insertions(+), 20 deletions(-) >> This seems like a nice cleanup to me. It's still odd that the general >> code has a special case for UART, but I guess the alternative is to >> duplicate the exact same logic for both the i2c and SPI drivers. I >> won't insist on that, though I wouldn't be opposed to it either. >> >> I guess one comment, though: should we also remove the code that >> messes with "SE_GENI_S_IRQ_EN" in geni_se_select_gpi_mode()? > > > Right now we have gpi-dma mode support for i2c and spi but not for uart. > > Even when gpi-dma support is added, uart driver's interrupt handler > would not be invoked so I believe it would be safe to drop that code > from geni_se_select_gpi_mode() too. > > I will post v2 dropping same after some more lookup. Looking at this once again, I am more inclined towards leaving alone gpi_mode() for now. It probably needs cleanup but we want to take that up at a later time. Meanwhile its not causing much harm as we don't switch modes dynamically for gpi case, so we are not losing much time there reading from and writing to registers. Please let know your thoughts. Thank you, Vijay/ > > -Vijay/ > > >> >> -Doug
Hi, On Tue, Jun 13, 2023 at 9:07 AM Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> wrote: > > Hi, > > > On 6/12/2023 7:09 PM, Vijaya Krishna Nivarthi wrote: > > Hi, > > > > Thank you very much for the review... > > > > > > On 6/7/2023 9:41 PM, Doug Anderson wrote: > >> Hi, > >> > >> On Fri, Jun 2, 2023 at 11:13 AM Vijaya Krishna Nivarthi > >> <quic_vnivarth@quicinc.com> wrote: > >>> The select_fifo/dma_mode() functions in geni driver enable/disable > >>> interrupts (secondary included) conditionally for non-uart modes, while > >>> uart is supposed to manage this internally. > >>> However, only uart uses secondary IRQs while spi, i2c do not care about > >>> these at all making their enablement (or disablement) totally > >>> unnecessary > >>> for these protos. > >>> > >>> Drop enabling/disabling secondary IRQs for non-uart modes. > >>> This doesn't solve any observed problem but only gets rid of code > >>> pieces > >>> that are not required. > >>> > >>> Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> > >>> --- > >>> drivers/soc/qcom/qcom-geni-se.c | 24 ++++-------------------- > >>> 1 file changed, 4 insertions(+), 20 deletions(-) > >> This seems like a nice cleanup to me. It's still odd that the general > >> code has a special case for UART, but I guess the alternative is to > >> duplicate the exact same logic for both the i2c and SPI drivers. I > >> won't insist on that, though I wouldn't be opposed to it either. > >> > >> I guess one comment, though: should we also remove the code that > >> messes with "SE_GENI_S_IRQ_EN" in geni_se_select_gpi_mode()? > > > > > > Right now we have gpi-dma mode support for i2c and spi but not for uart. > > > > Even when gpi-dma support is added, uart driver's interrupt handler > > would not be invoked so I believe it would be safe to drop that code > > from geni_se_select_gpi_mode() too. > > > > I will post v2 dropping same after some more lookup. > > > Looking at this once again, I am more inclined towards leaving alone > gpi_mode() for now. > > It probably needs cleanup but we want to take that up at a later time. > > Meanwhile its not causing much harm as we don't switch modes dynamically > for gpi case, so we are not losing much time there reading from and > writing to registers. > > Please let know your thoughts. It's not really about the time needed for the extra register writes, but just someone trying to understand the code who might be trying to figure out what bits are relevant. The bits related to the secondary sequencer's interrupts don't do anything useful when we're using the controller for i2c/spi, so why not delete them? -Doug
Hi, On 6/13/2023 11:27 PM, Doug Anderson wrote: > Hi, > > On Tue, Jun 13, 2023 at 9:07 AM Vijaya Krishna Nivarthi > <quic_vnivarth@quicinc.com> wrote: >> Hi, >> >> >> On 6/12/2023 7:09 PM, Vijaya Krishna Nivarthi wrote: >>> Hi, >>> >>> Thank you very much for the review... >>> >>> >>> On 6/7/2023 9:41 PM, Doug Anderson wrote: >>>> Hi, >>>> >>>> On Fri, Jun 2, 2023 at 11:13 AM Vijaya Krishna Nivarthi >>>> <quic_vnivarth@quicinc.com> wrote: >>>>> The select_fifo/dma_mode() functions in geni driver enable/disable >>>>> interrupts (secondary included) conditionally for non-uart modes, while >>>>> uart is supposed to manage this internally. >>>>> However, only uart uses secondary IRQs while spi, i2c do not care about >>>>> these at all making their enablement (or disablement) totally >>>>> unnecessary >>>>> for these protos. >>>>> >>>>> Drop enabling/disabling secondary IRQs for non-uart modes. >>>>> This doesn't solve any observed problem but only gets rid of code >>>>> pieces >>>>> that are not required. >>>>> >>>>> Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> >>>>> --- >>>>> drivers/soc/qcom/qcom-geni-se.c | 24 ++++-------------------- >>>>> 1 file changed, 4 insertions(+), 20 deletions(-) >>>> This seems like a nice cleanup to me. It's still odd that the general >>>> code has a special case for UART, but I guess the alternative is to >>>> duplicate the exact same logic for both the i2c and SPI drivers. I >>>> won't insist on that, though I wouldn't be opposed to it either. >>>> >>>> I guess one comment, though: should we also remove the code that >>>> messes with "SE_GENI_S_IRQ_EN" in geni_se_select_gpi_mode()? >>> >>> Right now we have gpi-dma mode support for i2c and spi but not for uart. >>> >>> Even when gpi-dma support is added, uart driver's interrupt handler >>> would not be invoked so I believe it would be safe to drop that code >>> from geni_se_select_gpi_mode() too. >>> >>> I will post v2 dropping same after some more lookup. >> >> Looking at this once again, I am more inclined towards leaving alone >> gpi_mode() for now. >> >> It probably needs cleanup but we want to take that up at a later time. >> >> Meanwhile its not causing much harm as we don't switch modes dynamically >> for gpi case, so we are not losing much time there reading from and >> writing to registers. >> >> Please let know your thoughts. > It's not really about the time needed for the extra register writes, > but just someone trying to understand the code who might be trying to > figure out what bits are relevant. The bits related to the secondary > sequencer's interrupts don't do anything useful when we're using the > controller for i2c/spi, so why not delete them? Agreed the s_irqs are not useful for spi/i2c but Right now I am not really sure how uart + gsi mode is going to look like. So how about we move the part that messes with s_irq in gpi_mode() into a *if(proto == GENI_SE_UART)* conditional? Understand we are adding to weirdness but Would that be ok for now? thank you, Vijay/ > > -Doug
Hi, On Tue, Jun 13, 2023 at 11:24 AM Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> wrote: > > Hi, > > > On 6/13/2023 11:27 PM, Doug Anderson wrote: > > Hi, > > > > On Tue, Jun 13, 2023 at 9:07 AM Vijaya Krishna Nivarthi > > <quic_vnivarth@quicinc.com> wrote: > >> Hi, > >> > >> > >> On 6/12/2023 7:09 PM, Vijaya Krishna Nivarthi wrote: > >>> Hi, > >>> > >>> Thank you very much for the review... > >>> > >>> > >>> On 6/7/2023 9:41 PM, Doug Anderson wrote: > >>>> Hi, > >>>> > >>>> On Fri, Jun 2, 2023 at 11:13 AM Vijaya Krishna Nivarthi > >>>> <quic_vnivarth@quicinc.com> wrote: > >>>>> The select_fifo/dma_mode() functions in geni driver enable/disable > >>>>> interrupts (secondary included) conditionally for non-uart modes, while > >>>>> uart is supposed to manage this internally. > >>>>> However, only uart uses secondary IRQs while spi, i2c do not care about > >>>>> these at all making their enablement (or disablement) totally > >>>>> unnecessary > >>>>> for these protos. > >>>>> > >>>>> Drop enabling/disabling secondary IRQs for non-uart modes. > >>>>> This doesn't solve any observed problem but only gets rid of code > >>>>> pieces > >>>>> that are not required. > >>>>> > >>>>> Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> > >>>>> --- > >>>>> drivers/soc/qcom/qcom-geni-se.c | 24 ++++-------------------- > >>>>> 1 file changed, 4 insertions(+), 20 deletions(-) > >>>> This seems like a nice cleanup to me. It's still odd that the general > >>>> code has a special case for UART, but I guess the alternative is to > >>>> duplicate the exact same logic for both the i2c and SPI drivers. I > >>>> won't insist on that, though I wouldn't be opposed to it either. > >>>> > >>>> I guess one comment, though: should we also remove the code that > >>>> messes with "SE_GENI_S_IRQ_EN" in geni_se_select_gpi_mode()? > >>> > >>> Right now we have gpi-dma mode support for i2c and spi but not for uart. > >>> > >>> Even when gpi-dma support is added, uart driver's interrupt handler > >>> would not be invoked so I believe it would be safe to drop that code > >>> from geni_se_select_gpi_mode() too. > >>> > >>> I will post v2 dropping same after some more lookup. > >> > >> Looking at this once again, I am more inclined towards leaving alone > >> gpi_mode() for now. > >> > >> It probably needs cleanup but we want to take that up at a later time. > >> > >> Meanwhile its not causing much harm as we don't switch modes dynamically > >> for gpi case, so we are not losing much time there reading from and > >> writing to registers. > >> > >> Please let know your thoughts. > > It's not really about the time needed for the extra register writes, > > but just someone trying to understand the code who might be trying to > > figure out what bits are relevant. The bits related to the secondary > > sequencer's interrupts don't do anything useful when we're using the > > controller for i2c/spi, so why not delete them? > > > Agreed the s_irqs are not useful for spi/i2c but Right now I am not > really sure how uart + gsi mode is going to look like. > > So how about we move the part that messes with s_irq in gpi_mode() into > a *if(proto == GENI_SE_UART)* conditional? > > Understand we are adding to weirdness but Would that be ok for now? For the non-GPI DMA path and for the PIO path we don't touch the "S_IRQ" for UART either (we don't touch any IRQs for the UART). ...so it doesn't seem right to be tweaking with the S_IRQ for UART. I would say delete it and if/when the UART needs GPI mode then we can figure out what to do. I'd actually wonder if GPI will ever be implemented for UART anyway. The whole idea of GPI is to allow sharing a port between more than one user. Each user could submit a "transaction" and they'd get the port for the duration of that transaction. After the transaction was done then another user would be able to grab the port. Typically UART isn't used like this. I'm not saying that it couldn't be done, but just saying that it would be a pretty non-standard way of using a UART... -Doug
Hi, On 6/14/2023 12:44 AM, Doug Anderson wrote: > Hi, > > On Tue, Jun 13, 2023 at 11:24 AM Vijaya Krishna Nivarthi > <quic_vnivarth@quicinc.com> wrote: >> Hi, >> >> >> On 6/13/2023 11:27 PM, Doug Anderson wrote: >>> Hi, >>> >>> On Tue, Jun 13, 2023 at 9:07 AM Vijaya Krishna Nivarthi >>> <quic_vnivarth@quicinc.com> wrote: >>>> Hi, >>>> >>>> >>>> On 6/12/2023 7:09 PM, Vijaya Krishna Nivarthi wrote: >>>>> Hi, >>>>> >>>>> Thank you very much for the review... >>>>> >>>>> >>>>> On 6/7/2023 9:41 PM, Doug Anderson wrote: >>>>>> Hi, >>>>>> >>>>>> On Fri, Jun 2, 2023 at 11:13 AM Vijaya Krishna Nivarthi >>>>>> <quic_vnivarth@quicinc.com> wrote: >>>>>>> The select_fifo/dma_mode() functions in geni driver enable/disable >>>>>>> interrupts (secondary included) conditionally for non-uart modes, while >>>>>>> uart is supposed to manage this internally. >>>>>>> However, only uart uses secondary IRQs while spi, i2c do not care about >>>>>>> these at all making their enablement (or disablement) totally >>>>>>> unnecessary >>>>>>> for these protos. >>>>>>> >>>>>>> Drop enabling/disabling secondary IRQs for non-uart modes. >>>>>>> This doesn't solve any observed problem but only gets rid of code >>>>>>> pieces >>>>>>> that are not required. >>>>>>> >>>>>>> Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> >>>>>>> --- >>>>>>> drivers/soc/qcom/qcom-geni-se.c | 24 ++++-------------------- >>>>>>> 1 file changed, 4 insertions(+), 20 deletions(-) >>>>>> This seems like a nice cleanup to me. It's still odd that the general >>>>>> code has a special case for UART, but I guess the alternative is to >>>>>> duplicate the exact same logic for both the i2c and SPI drivers. I >>>>>> won't insist on that, though I wouldn't be opposed to it either. >>>>>> >>>>>> I guess one comment, though: should we also remove the code that >>>>>> messes with "SE_GENI_S_IRQ_EN" in geni_se_select_gpi_mode()? >>>>> Right now we have gpi-dma mode support for i2c and spi but not for uart. >>>>> >>>>> Even when gpi-dma support is added, uart driver's interrupt handler >>>>> would not be invoked so I believe it would be safe to drop that code >>>>> from geni_se_select_gpi_mode() too. >>>>> >>>>> I will post v2 dropping same after some more lookup. >>>> Looking at this once again, I am more inclined towards leaving alone >>>> gpi_mode() for now. >>>> >>>> It probably needs cleanup but we want to take that up at a later time. >>>> >>>> Meanwhile its not causing much harm as we don't switch modes dynamically >>>> for gpi case, so we are not losing much time there reading from and >>>> writing to registers. >>>> >>>> Please let know your thoughts. >>> It's not really about the time needed for the extra register writes, >>> but just someone trying to understand the code who might be trying to >>> figure out what bits are relevant. The bits related to the secondary >>> sequencer's interrupts don't do anything useful when we're using the >>> controller for i2c/spi, so why not delete them? >> >> Agreed the s_irqs are not useful for spi/i2c but Right now I am not >> really sure how uart + gsi mode is going to look like. >> >> So how about we move the part that messes with s_irq in gpi_mode() into >> a *if(proto == GENI_SE_UART)* conditional? >> >> Understand we are adding to weirdness but Would that be ok for now? > For the non-GPI DMA path and for the PIO path we don't touch the > "S_IRQ" for UART either (we don't touch any IRQs for the UART). ...so > it doesn't seem right to be tweaking with the S_IRQ for UART. I would > say delete it and if/when the UART needs GPI mode then we can figure > out what to do. > > I'd actually wonder if GPI will ever be implemented for UART anyway. > The whole idea of GPI is to allow sharing a port between more than one > user. Each user could submit a "transaction" and they'd get the port > for the duration of that transaction. After the transaction was done > then another user would be able to grab the port. Typically UART isn't > used like this. I'm not saying that it couldn't be done, but just > saying that it would be a pretty non-standard way of using a UART... Agreed on both. Uploading v2 dropping from gpi_mode() Thank you. -Vijay/ > > -Doug
diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index 795a2e1..7111661 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -281,27 +281,14 @@ static void geni_se_select_fifo_mode(struct geni_se *se) geni_se_irq_clear(se); - /* - * The RX path for the UART is asynchronous and so needs more - * complex logic for enabling / disabling its interrupts. - * - * Specific notes: - * - The done and TX-related interrupts are managed manually. - * - We don't RX from the main sequencer (we use the secondary) so - * we don't need the RX-related interrupts enabled in the main - * sequencer for UART. - */ + /* UART driver manages enabling / disabling interrupts internally */ if (proto != GENI_SE_UART) { + /* Non-UART use only primary sequencer so dont bother about S_IRQ */ val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN; val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; if (val != val_old) writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); - - val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); - val |= S_CMD_DONE_EN; - if (val != val_old) - writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); } val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); @@ -317,17 +304,14 @@ static void geni_se_select_dma_mode(struct geni_se *se) geni_se_irq_clear(se); + /* UART driver manages enabling / disabling interrupts internally */ if (proto != GENI_SE_UART) { + /* Non-UART use only primary sequencer so dont bother about S_IRQ */ val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); val &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); if (val != val_old) writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); - - val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); - val &= ~S_CMD_DONE_EN; - if (val != val_old) - writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); } val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);