diff mbox series

[v1] RISC-V: Fix one potential test failure for RVV vsetvl

Message ID 20230612121844.1412921-1-pan2.li@intel.com
State Unresolved
Headers
Series [v1] RISC-V: Fix one potential test failure for RVV vsetvl |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Li, Pan2 via Gcc-patches June 12, 2023, 12:18 p.m. UTC 
  From: Pan Li <pan2.li@intel.com>

The test will fail on below command with multi-thread like below.  However,
it comes from one missed "Oz" option when check vsetvl.

make -j $(nproc) report RUNTESTFLAGS="rvv.exp riscv.exp"

To some reason, this failure cannot be reproduced by RUNTESTFLAGS="rvv.exp"
or make without -j option. We would like to fix it and root cause the
reason later.

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/vsetvl/vsetvl-23.c: Adjust test checking.
---
 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Kito Cheng June 12, 2023, 12:29 p.m. UTC | #1 
OK for this patch, and I am thinking we should adjust rvv.exp to
just exclude -O0, -Os and -Oz for some testcases run to simplify many
testcases.


On Mon, Jun 12, 2023 at 8:20 PM Pan Li via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> The test will fail on below command with multi-thread like below.  However,
> it comes from one missed "Oz" option when check vsetvl.
>
> make -j $(nproc) report RUNTESTFLAGS="rvv.exp riscv.exp"
>
> To some reason, this failure cannot be reproduced by RUNTESTFLAGS="rvv.exp"
> or make without -j option. We would like to fix it and root cause the
> reason later.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/vsetvl/vsetvl-23.c: Adjust test checking.
> ---
>  gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
> index 66c90ac10e7..f3420be8ab6 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
> @@ -34,4 +34,4 @@ void f(int8_t *base, int8_t *out, size_t vl, size_t m, size_t k) {
>  /* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*4} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
>  /* { dg-final { scan-assembler-times {srli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*8} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
>  /* { dg-final { scan-assembler-times {vsetvli} 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
> -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
> --
> 2.34.1
>
Li, Pan2 via Gcc-patches June 12, 2023, 2:13 p.m. UTC | #2 
Committed, thanks Kito.

Sounds good to me. Not sure if there are some tests focus on -O0/Os/Oz, we can refine this in another PATCH.

Pan

-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com> 
Sent: Monday, June 12, 2023 8:30 PM
To: Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; rdapp.gcc@gmail.com; jeffreyalaw@gmail.com; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v1] RISC-V: Fix one potential test failure for RVV vsetvl

OK for this patch, and I am thinking we should adjust rvv.exp to just exclude -O0, -Os and -Oz for some testcases run to simplify many testcases.


On Mon, Jun 12, 2023 at 8:20 PM Pan Li via Gcc-patches <gcc-patches@gcc.gnu.org> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> The test will fail on below command with multi-thread like below.  
> However, it comes from one missed "Oz" option when check vsetvl.
>
> make -j $(nproc) report RUNTESTFLAGS="rvv.exp riscv.exp"
>
> To some reason, this failure cannot be reproduced by RUNTESTFLAGS="rvv.exp"
> or make without -j option. We would like to fix it and root cause the 
> reason later.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/vsetvl/vsetvl-23.c: Adjust test checking.
> ---
>  gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
> index 66c90ac10e7..f3420be8ab6 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
> @@ -34,4 +34,4 @@ void f(int8_t *base, int8_t *out, size_t vl, size_t 
> m, size_t k) {
>  /* { dg-final { scan-assembler-times 
> {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*4} 1 { target { no-opts "-O0" 
> no-opts "-g" no-opts "-funroll-loops" } } } } */
>  /* { dg-final { scan-assembler-times 
> {srli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*8} 1 { target { no-opts "-O0" 
> no-opts "-g" no-opts "-funroll-loops" } } } } */
>  /* { dg-final { scan-assembler-times {vsetvli} 5 { target { no-opts 
> "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts 
> "-funroll-loops" } } } } */
> -/* { dg-final { scan-assembler-times 
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 5 { target { 
> no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } 
> } } */
> +/* { dg-final { scan-assembler-times 
> +{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 5 { target 
> +{ no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts 
> +"-funroll-loops" } } } } */
> --
> 2.34.1
>
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
index 66c90ac10e7..f3420be8ab6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
@@ -34,4 +34,4 @@  void f(int8_t *base, int8_t *out, size_t vl, size_t m, size_t k) {
 /* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*4} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
 /* { dg-final { scan-assembler-times {srli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*8} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli} 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */