Message ID | 20230607012355.442707-1-suhui@nfschina.com |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp3786183vqr; Tue, 6 Jun 2023 18:44:55 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5r/FHkBoje0Y8t43AhgFWwTR3DTeHcoQLPV4ncG9g3NIXa/0WGB1YIkVBtOFOc7LMAcjp0 X-Received: by 2002:aca:1908:0:b0:39c:464f:a55f with SMTP id l8-20020aca1908000000b0039c464fa55fmr3998456oii.24.1686102294878; Tue, 06 Jun 2023 18:44:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686102294; cv=none; d=google.com; s=arc-20160816; b=LHRGd5gsKB/Cez/DSO5tL7DnHfdAzurK2C5EbQpNb8pt3wGLtoIzQ/VN52+1f47zWy oVgD4mU3ICOJ7CYMaZorB4S0jxapShlDsMNR/VfikzSqWuJ+6Hc0a008kHDic9SP3j2d jJSbj0EzBEWjhFS60RPewtzEDl7C6fpHXzszK0+k46mBEpnz/Oz58LMAfdvIYgH6JRV+ G42JNk95D4s/A5D3GBebtHG0sJ3C76cssTmKUONLxwIIPVw7aPAjCU9vSdtIAHDd1bZb moO/t0YQ8wtOkHLXsLbo6jhOjJAC77JXExr/a415GUBgoWzL1Pvmz2/VNCNgcXFtl3Ht H8mA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=c4yBMrm9SC5ZggylCf8SxLLY8H53Tm6YGUmMSGXwhAU=; b=ojOMxsC6aNas7uZG/QdDJNIQ3PSSupUJZIC6niEze5NPx3fTX5vQWCmkc7Yn9IpgJq uwLWlC/DxCOxB7uJGHcTLCY5tX/UoVlctVX8AgWscjdsi1fcCrykvN9NytjvZB3xk7Hy amj5m+QskqN6i/TbVrZ2tU0L4F9Yi7O27fIkEzaIczDla08RiQMSevKqoMSIJpzh9LI9 9AzmvE/MHQl6oCJB+0Vgrnx40iEezi2KrBlpGGYYuOLjT10BYNIf9maJPj5pHcEWoXgb X2plzYnkSgX8XrynLjG06P8LUZ1YApo7G5e7toE3ropoaDHu9C0/XjfQYGoeuwebrvMI cu4g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 18-20020a170902c11200b001b06fa86b08si7917145pli.412.2023.06.06.18.44.39; Tue, 06 Jun 2023 18:44:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234123AbjFGBZB (ORCPT <rfc822;literming00@gmail.com> + 99 others); Tue, 6 Jun 2023 21:25:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58860 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240121AbjFGBYx (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Tue, 6 Jun 2023 21:24:53 -0400 Received: from mail.nfschina.com (unknown [42.101.60.195]) by lindbergh.monkeyblade.net (Postfix) with SMTP id 6AC3A172E for <linux-kernel@vger.kernel.org>; Tue, 6 Jun 2023 18:24:52 -0700 (PDT) Received: from localhost.localdomain (unknown [180.167.10.98]) by mail.nfschina.com (Maildata Gateway V2.8.8) with ESMTPA id 596111800F838B; Wed, 7 Jun 2023 09:24:03 +0800 (CST) X-MD-Sfrom: suhui@nfschina.com X-MD-SrcIP: 180.167.10.98 From: Su Hui <suhui@nfschina.com> To: Douglas Anderson <dianders@chromium.org>, Andrzej Hajda <andrzej.hajda@intel.com>, Neil Armstrong <neil.armstrong@linaro.org>, Robert Foss <rfoss@kernel.org>, Laurent Pinchart <Laurent.pinchart@ideasonboard.com>, Jonas Karlman <jonas@kwiboo.se>, Jernej Skrabec <jernej.skrabec@gmail.com>, David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch> Cc: andersson@kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Su Hui <suhui@nfschina.com> Subject: [PATCH v2] drm/bridge: ti-sn65dsi86: Avoid possible buffer overflow Date: Wed, 7 Jun 2023 09:23:55 +0800 Message-Id: <20230607012355.442707-1-suhui@nfschina.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,RDNS_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768006399725126304?= X-GMAIL-MSGID: =?utf-8?q?1768006399725126304?= |
Series |
[v2] drm/bridge: ti-sn65dsi86: Avoid possible buffer overflow
|
|
Commit Message
Su Hui
June 7, 2023, 1:23 a.m. UTC
Smatch error:buffer overflow 'ti_sn_bridge_refclk_lut' 5 <= 5.
Fixes: cea86c5bb442 ("drm/bridge: ti-sn65dsi86: Implement the pwm_chip")
Signed-off-by: Su Hui <suhui@nfschina.com>
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Comments
Hi, On Tue, Jun 6, 2023 at 6:25 PM Su Hui <suhui@nfschina.com> wrote: > > Smatch error:buffer overflow 'ti_sn_bridge_refclk_lut' 5 <= 5. > > Fixes: cea86c5bb442 ("drm/bridge: ti-sn65dsi86: Implement the pwm_chip") > Signed-off-by: Su Hui <suhui@nfschina.com> > --- > drivers/gpu/drm/bridge/ti-sn65dsi86.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > index 7a748785c545..bb88406495e9 100644 > --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > @@ -305,7 +305,7 @@ static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata) > * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG, > * regardless of its actual sourcing. > */ > - pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i]; > + pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i < refclk_lut_size ? i : 1]; This looks more correct, but it really needs a comment since it's totally not obviously what you're doing here. IMO the best solution here is to update "i" right after the for loop and have a comment about the datasheet saying that "1" is the default rate so we'll fall back to that if we couldn't find a match. Moving it to right after the for loop will change the value written into the registers, but that's fine and makes it clearer what's happening. -Doug On Tue, Jun 6, 2023 at 6:25 PM Su Hui <suhui@nfschina.com> wrote: > > Smatch error:buffer overflow 'ti_sn_bridge_refclk_lut' 5 <= 5. > > Fixes: cea86c5bb442 ("drm/bridge: ti-sn65dsi86: Implement the pwm_chip") > Signed-off-by: Su Hui <suhui@nfschina.com> > --- > drivers/gpu/drm/bridge/ti-sn65dsi86.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > index 7a748785c545..bb88406495e9 100644 > --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > @@ -305,7 +305,7 @@ static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata) > * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG, > * regardless of its actual sourcing. > */ > - pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i]; > + pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i < refclk_lut_size ? i : 1]; > } > > static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata) > -- > 2.30.2 >
On 2023/6/7 22:03, Doug Anderson wrote: > Hi, > > On Tue, Jun 6, 2023 at 6:25 PM Su Hui <suhui@nfschina.com> wrote: >> Smatch error:buffer overflow 'ti_sn_bridge_refclk_lut' 5 <= 5. >> >> Fixes: cea86c5bb442 ("drm/bridge: ti-sn65dsi86: Implement the pwm_chip") >> Signed-off-by: Su Hui <suhui@nfschina.com> >> --- >> drivers/gpu/drm/bridge/ti-sn65dsi86.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c >> index 7a748785c545..bb88406495e9 100644 >> --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c >> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c >> @@ -305,7 +305,7 @@ static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata) >> * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG, >> * regardless of its actual sourcing. >> */ >> - pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i]; >> + pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i < refclk_lut_size ? i : 1]; > This looks more correct, but it really needs a comment since it's > totally not obviously what you're doing here. IMO the best solution > here is to update "i" right after the for loop and have a comment > about the datasheet saying that "1" is the default rate so we'll fall > back to that if we couldn't find a match. Moving it to right after the > for loop will change the value written into the registers, but that's > fine and makes it clearer what's happening. Got it. Add some comment and move the code up. I will send patch v3 soon. Thanks for your suggestion again :) . Su Hui > > -Doug
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index 7a748785c545..bb88406495e9 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -305,7 +305,7 @@ static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata) * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG, * regardless of its actual sourcing. */ - pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i]; + pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i < refclk_lut_size ? i : 1]; } static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata)