[v2] dt-bindings: pinctrl: update uart/mmc bindings for MT7986 SoC
Commit Message
From: Frank Wunderlich <frank-w@public-files.de>
Add new splitted uart pins and emmc_51
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
v2:
- wrap on col 80
---
.../pinctrl/mediatek,mt7986-pinctrl.yaml | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
Comments
On 25/10/2022 03:02, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@public-files.de>
>
> Add new splitted uart pins and emmc_51
>
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
Hi
> Gesendet: Dienstag, 25. Oktober 2022 um 20:35 Uhr
> Von: "Krzysztof Kozlowski" <krzysztof.kozlowski@linaro.org>
> Betreff: Re: [PATCH v2] dt-bindings: pinctrl: update uart/mmc bindings for MT7986 SoC
>
> On 25/10/2022 03:02, Frank Wunderlich wrote:
> > From: Frank Wunderlich <frank-w@public-files.de>
> >
> > Add new splitted uart pins and emmc_51
> >
> > Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
>
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
after talking with MTK for the emmc pinctrl settings (custom pull-up) they suggested me to change
binding to fix other emmc-values and allow multiple (2) uart-items
so on top of this patch
then:
properties:
groups:
- enum: [emmc, emmc_rst, emmc_51]
+ enum: [emmc_45, emmc_51]
- if:
properties:
function:
@@ -231,10 +231,12 @@ patternProperties:
then:
properties:
groups:
- enum: [uart1_0, uart1_rx_tx, uart1_cts_rts, uart1_1,
- uart1_2_rx_tx, uart1_2_cts_rts, uart1_3_rx_tx,
- uart1_3_cts_rts, uart2_0_rx_tx, uart2_0_cts_rts,
- uart2_1, uart0, uart1, uart2]
+ items:
+ enum: [uart1_0, uart1_rx_tx, uart1_cts_rts, uart1_1,
+ uart1_2_rx_tx, uart1_2_cts_rts, uart1_3_rx_tx,
+ uart1_3_cts_rts, uart2_0_rx_tx, uart2_0_cts_rts,
+ uart2_1, uart0, uart1, uart2]
+ maxItems: 2
i would squash these changes and send as v3 or should i send an extra-patch?
regards Frank
On Fri, Nov 4, 2022 at 5:04 PM Frank Wunderlich <frank-w@public-files.de> wrote:
> > Gesendet: Dienstag, 25. Oktober 2022 um 20:35 Uhr
> > Von: "Krzysztof Kozlowski" <krzysztof.kozlowski@linaro.org>
> > Betreff: Re: [PATCH v2] dt-bindings: pinctrl: update uart/mmc bindings for MT7986 SoC
> >
> > On 25/10/2022 03:02, Frank Wunderlich wrote:
> > > From: Frank Wunderlich <frank-w@public-files.de>
> > >
> > > Add new splitted uart pins and emmc_51
> > >
> > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> >
> >
> > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> after talking with MTK for the emmc pinctrl settings (custom pull-up) they suggested me to change
> binding to fix other emmc-values and allow multiple (2) uart-items
>
> so on top of this patch
>
> then:
> properties:
> groups:
> - enum: [emmc, emmc_rst, emmc_51]
> + enum: [emmc_45, emmc_51]
> - if:
> properties:
> function:
> @@ -231,10 +231,12 @@ patternProperties:
> then:
> properties:
> groups:
> - enum: [uart1_0, uart1_rx_tx, uart1_cts_rts, uart1_1,
> - uart1_2_rx_tx, uart1_2_cts_rts, uart1_3_rx_tx,
> - uart1_3_cts_rts, uart2_0_rx_tx, uart2_0_cts_rts,
> - uart2_1, uart0, uart1, uart2]
> + items:
> + enum: [uart1_0, uart1_rx_tx, uart1_cts_rts, uart1_1,
> + uart1_2_rx_tx, uart1_2_cts_rts, uart1_3_rx_tx,
> + uart1_3_cts_rts, uart2_0_rx_tx, uart2_0_cts_rts,
> + uart2_1, uart0, uart1, uart2]
> + maxItems: 2
>
> i would squash these changes and send as v3 or should i send an extra-patch?
Squash and send av v3 if you haven't already! Easiest for me.
Yours,
Linus Walleij
Am 8. November 2022 15:50:44 MEZ schrieb Linus Walleij <linus.walleij@linaro.org>:
>Squash and send av v3 if you haven't already! Easiest for me.
>
>Yours,
>Linus Walleij
Have already here:
https://patchwork.kernel.org/project/linux-mediatek/patch/20221106080114.7426-3-linux@fw-web.de/
regards Frank
@@ -87,6 +87,8 @@ patternProperties:
"wifi_led" "led" 1, 2
"i2c" "i2c" 3, 4
"uart1_0" "uart" 7, 8, 9, 10
+ "uart1_rx_tx" "uart" 42, 43
+ "uart1_cts_rts" "uart" 44, 45
"pcie_clk" "pcie" 9
"pcie_wake" "pcie" 10
"spi1_0" "spi" 11, 12, 13, 14
@@ -98,9 +100,11 @@ patternProperties:
"emmc_45" "emmc" 22, 23, 24, 25, 26, 27, 28, 29, 30,
31, 32
"spi1_1" "spi" 23, 24, 25, 26
- "uart1_2" "uart" 29, 30, 31, 32
+ "uart1_2_rx_tx" "uart" 29, 30
+ "uart1_2_cts_rts" "uart" 31, 32
"uart1_1" "uart" 23, 24, 25, 26
- "uart2_0" "uart" 29, 30, 31, 32
+ "uart2_0_rx_tx" "uart" 29, 30
+ "uart2_0_cts_rts" "uart" 31, 32
"spi0" "spi" 33, 34, 35, 36
"spi0_wp_hold" "spi" 37, 38
"uart1_3_rx_tx" "uart" 35, 36
@@ -157,7 +161,7 @@ patternProperties:
then:
properties:
groups:
- enum: [emmc, emmc_rst]
+ enum: [emmc, emmc_rst, emmc_51]
- if:
properties:
function:
@@ -227,8 +231,10 @@ patternProperties:
then:
properties:
groups:
- enum: [uart1_0, uart1_1, uart1_2, uart1_3_rx_tx,
- uart1_3_cts_rts, uart2_0, uart2_1, uart0, uart1, uart2]
+ enum: [uart1_0, uart1_rx_tx, uart1_cts_rts, uart1_1,
+ uart1_2_rx_tx, uart1_2_cts_rts, uart1_3_rx_tx,
+ uart1_3_cts_rts, uart2_0_rx_tx, uart2_0_cts_rts,
+ uart2_1, uart0, uart1, uart2]
- if:
properties:
function: