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Fri, 02 Jun 2023 11:04:16 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 352B4F5u001458 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 2 Jun 2023 11:04:15 GMT Received: from varda-linux.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 2 Jun 2023 04:04:09 -0700 From: Varadarajan Narayanan <quic_varada@quicinc.com> To: <agross@kernel.org>, <andersson@kernel.org>, <konrad.dybcio@linaro.org>, <amitk@kernel.org>, <thara.gopinath@gmail.com>, <rafael@kernel.org>, <daniel.lezcano@linaro.org>, <rui.zhang@intel.com>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>, <linux-arm-msm@vger.kernel.org>, <linux-pm@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org> CC: Varadarajan Narayanan <quic_varada@quicinc.com>, Praveenkumar I <quic_ipkumar@quicinc.com> Subject: [PATCH v5 2/3] arm64: dts: qcom: ipq9574: add tsens node Date: Fri, 2 Jun 2023 16:33:51 +0530 Message-ID: <dcb682766d8e01f8f4eed7f26fcbfba1b4091137.1685703605.git.quic_varada@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <cover.1685703605.git.quic_varada@quicinc.com> References: <cover.1685703605.git.quic_varada@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 4wkLciFr97-XHwFvuPGweJhSQVezMbqs X-Proofpoint-GUID: 4wkLciFr97-XHwFvuPGweJhSQVezMbqs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-02_07,2023-06-02_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=958 lowpriorityscore=0 malwarescore=0 adultscore=0 mlxscore=0 bulkscore=0 clxscore=1015 spamscore=0 suspectscore=0 phishscore=0 impostorscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2306020081 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767588897390094143?= X-GMAIL-MSGID: =?utf-8?q?1767588897390094143?= |
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Enable IPQ9574 TSENS support
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Commit Message
Varadarajan Narayanan
June 2, 2023, 11:03 a.m. UTC
IPQ9574 has a tsens v2.3.1 peripheral which monitors temperatures around the various subsystems on the die. Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> --- [v5]: Incorporate review comments [v2]: Add "qcom,ipq8074-tsens" as fallback compatible --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
Comments
On 2.06.2023 13:03, Varadarajan Narayanan wrote: > IPQ9574 has a tsens v2.3.1 peripheral which monitors temperatures > around the various subsystems on the die. > > Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com> > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > [v5]: > Incorporate review comments "fix bug" is too vague.. > > [v2]: > Add "qcom,ipq8074-tsens" as fallback compatible > --- > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > index 0baeb10..cda3fd4 100644 > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > @@ -206,6 +206,16 @@ > #size-cells = <1>; > }; > > + tsens: thermal-sensor@4a9000 { > + compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens"; > + reg = <0x004a9000 0x1000>, /* TM */ > + <0x004a8000 0x1000>; /* SROT */ The comments are unnecessary, we've been copypasting them from SoC to SoC but it's time we stop. With that: Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "combined"; > + #qcom,sensors = <16>; > + #thermal-sensor-cells = <1>; > + }; > + > tlmm: pinctrl@1000000 { > compatible = "qcom,ipq9574-tlmm"; > reg = <0x01000000 0x300000>;
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 0baeb10..cda3fd4 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -206,6 +206,16 @@ #size-cells = <1>; }; + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens"; + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "combined"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq9574-tlmm"; reg = <0x01000000 0x300000>;