diff mbox series

[net-next,v7,5/5] ARM: dts: qcom: ipq4019: Add description for the IPQESS Ethernet controller

Message ID 20221104142746.350468-6-maxime.chevallier@bootlin.com
State New
Headers
Series net: ipqess: introduce Qualcomm IPQESS driver |

Commit Message

Maxime Chevallier Nov. 4, 2022, 2:27 p.m. UTC 
  The Qualcomm IPQ4019 includes an internal 5 ports switch, which is
connected to the CPU through the internal IPQESS Ethernet controller.

Add support for this internal interface, which is internally connected to a
modified version of the QCA8K Ethernet switch.

This Ethernet controller only support a specific internal interface mode
for connection to the switch.

Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
V6->V7:
 - No Changes
V5->V6:
 - Removed extra blank lines
 - Put the status property last
V4->V5:
 - Reword the commit log
V3->V4:
 - No Changes
V2->V3:
 - No Changes
V1->V2:
 - Added clock and resets

 arch/arm/boot/dts/qcom-ipq4019.dtsi | 44 +++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

Comments

Krzysztof Kozlowski Nov. 4, 2022, 2:31 p.m. UTC | #1 
On 04/11/2022 10:27, Maxime Chevallier wrote:
> The Qualcomm IPQ4019 includes an internal 5 ports switch, which is
> connected to the CPU through the internal IPQESS Ethernet controller.
> 
> Add support for this internal interface, which is internally connected to a
> modified version of the QCA8K Ethernet switch.
> 
> This Ethernet controller only support a specific internal interface mode
> for connection to the switch.
> 
> Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> V6->V7:
>  - No Changes
> V5->V6:
>  - Removed extra blank lines
>  - Put the status property last
> V4->V5:
>  - Reword the commit log
> V3->V4:
>  - No Changes
> V2->V3:
>  - No Changes
> V1->V2:
>  - Added clock and resets
> 
>  arch/arm/boot/dts/qcom-ipq4019.dtsi | 44 +++++++++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> index b23591110bd2..5fa1af147df9 100644
> --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> @@ -38,6 +38,7 @@ aliases {
>  		spi1 = &blsp1_spi2;
>  		i2c0 = &blsp1_i2c3;
>  		i2c1 = &blsp1_i2c4;
> +		ethernet0 = &gmac;

Hm, I have doubts about this one. Why alias is needed and why it is a
property of a SoC? Not every board has Ethernet enabled, so this looks
like board property.

I also wonder why do you need it at all?

Best regards,
Krzysztof
Vladimir Oltean Nov. 4, 2022, 2:32 p.m. UTC | #2 
On Fri, Nov 04, 2022 at 10:31:06AM -0400, Krzysztof Kozlowski wrote:
> > diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> > index b23591110bd2..5fa1af147df9 100644
> > --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
> > +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> > @@ -38,6 +38,7 @@ aliases {
> >  		spi1 = &blsp1_spi2;
> >  		i2c0 = &blsp1_i2c3;
> >  		i2c1 = &blsp1_i2c4;
> > +		ethernet0 = &gmac;
> 
> Hm, I have doubts about this one. Why alias is needed and why it is a
> property of a SoC? Not every board has Ethernet enabled, so this looks
> like board property.
> 
> I also wonder why do you need it at all?

In general, Ethernet aliases are needed so that the bootloader can fix
up the MAC address of each port's OF node with values it gets from the
U-Boot environment or an AT24 EEPROM or something like that.
Krzysztof Kozlowski Nov. 4, 2022, 3:08 p.m. UTC | #3 
On 04/11/2022 10:32, Vladimir Oltean wrote:
> On Fri, Nov 04, 2022 at 10:31:06AM -0400, Krzysztof Kozlowski wrote:
>>> diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
>>> index b23591110bd2..5fa1af147df9 100644
>>> --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
>>> +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
>>> @@ -38,6 +38,7 @@ aliases {
>>>  		spi1 = &blsp1_spi2;
>>>  		i2c0 = &blsp1_i2c3;
>>>  		i2c1 = &blsp1_i2c4;
>>> +		ethernet0 = &gmac;
>>
>> Hm, I have doubts about this one. Why alias is needed and why it is a
>> property of a SoC? Not every board has Ethernet enabled, so this looks
>> like board property.
>>
>> I also wonder why do you need it at all?
> 
> In general, Ethernet aliases are needed so that the bootloader can fix
> up the MAC address of each port's OF node with values it gets from the
> U-Boot environment or an AT24 EEPROM or something like that.

Assuming that's the case here, my other part of question remains - is
this property of SoC or board? The buses (SPI, I2C) are properties of
boards, even though were incorrectly put here. If the board has multiple
ethernets, the final ordering is the property of the board, not SoC. I
would assume that bootloader also configures the MAC address based on
the board config, not per SoC...

Best regards,
Krzysztof
Vladimir Oltean Nov. 4, 2022, 3:40 p.m. UTC | #4 
On Fri, Nov 04, 2022 at 11:08:07AM -0400, Krzysztof Kozlowski wrote:
> On 04/11/2022 10:32, Vladimir Oltean wrote:
> > On Fri, Nov 04, 2022 at 10:31:06AM -0400, Krzysztof Kozlowski wrote:
> >>> diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> >>> index b23591110bd2..5fa1af147df9 100644
> >>> --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
> >>> +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> >>> @@ -38,6 +38,7 @@ aliases {
> >>>  		spi1 = &blsp1_spi2;
> >>>  		i2c0 = &blsp1_i2c3;
> >>>  		i2c1 = &blsp1_i2c4;
> >>> +		ethernet0 = &gmac;
> >>
> >> Hm, I have doubts about this one. Why alias is needed and why it is a
> >> property of a SoC? Not every board has Ethernet enabled, so this looks
> >> like board property.
> >>
> >> I also wonder why do you need it at all?
> > 
> > In general, Ethernet aliases are needed so that the bootloader can fix
> > up the MAC address of each port's OF node with values it gets from the
> > U-Boot environment or an AT24 EEPROM or something like that.
> 
> Assuming that's the case here, my other part of question remains - is
> this property of SoC or board? The buses (SPI, I2C) are properties of
> boards, even though were incorrectly put here. If the board has multiple
> ethernets, the final ordering is the property of the board, not SoC. I
> would assume that bootloader also configures the MAC address based on
> the board config, not per SoC...

I don't disagree. On NXP LS1028A, we also have all aliases in board
device trees and not in the SoC dtsi.
Maxime Chevallier Nov. 4, 2022, 4:36 p.m. UTC | #5 
Hello Krzysztof, Vladimir,

On Fri, 4 Nov 2022 15:40:48 +0000
Vladimir Oltean <vladimir.oltean@nxp.com> wrote:

> On Fri, Nov 04, 2022 at 11:08:07AM -0400, Krzysztof Kozlowski wrote:
> > On 04/11/2022 10:32, Vladimir Oltean wrote:  
> > > On Fri, Nov 04, 2022 at 10:31:06AM -0400, Krzysztof Kozlowski
> > > wrote:  
> > >>> diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi
> > >>> b/arch/arm/boot/dts/qcom-ipq4019.dtsi index
> > >>> b23591110bd2..5fa1af147df9 100644 ---
> > >>> a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++
> > >>> b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -38,6 +38,7 @@ aliases
> > >>> { spi1 = &blsp1_spi2;
> > >>>  		i2c0 = &blsp1_i2c3;
> > >>>  		i2c1 = &blsp1_i2c4;
> > >>> +		ethernet0 = &gmac;  
> > >>
> > >> Hm, I have doubts about this one. Why alias is needed and why it
> > >> is a property of a SoC? Not every board has Ethernet enabled, so
> > >> this looks like board property.
> > >>
> > >> I also wonder why do you need it at all?  
> > > 
> > > In general, Ethernet aliases are needed so that the bootloader
> > > can fix up the MAC address of each port's OF node with values it
> > > gets from the U-Boot environment or an AT24 EEPROM or something
> > > like that.  
> > 
> > Assuming that's the case here, my other part of question remains -
> > is this property of SoC or board? The buses (SPI, I2C) are
> > properties of boards, even though were incorrectly put here. If the
> > board has multiple ethernets, the final ordering is the property of
> > the board, not SoC. I would assume that bootloader also configures
> > the MAC address based on the board config, not per SoC...  
> 
> I don't disagree. On NXP LS1028A, we also have all aliases in board
> device trees and not in the SoC dtsi.

You're right indeed, it was put there so that it's alongside the other
aliases, but it makes more sense to include it in the board file. I'll
respin with the alias removed.

Thanks,

Maxime
Robert Marko Nov. 4, 2022, 4:42 p.m. UTC | #6 
On Fri, Nov 4, 2022 at 3:28 PM Maxime Chevallier
<maxime.chevallier@bootlin.com> wrote:
>
> The Qualcomm IPQ4019 includes an internal 5 ports switch, which is
> connected to the CPU through the internal IPQESS Ethernet controller.
>
> Add support for this internal interface, which is internally connected to a
> modified version of the QCA8K Ethernet switch.
>
> This Ethernet controller only support a specific internal interface mode
> for connection to the switch.
>
> Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> V6->V7:
>  - No Changes
> V5->V6:
>  - Removed extra blank lines
>  - Put the status property last
> V4->V5:
>  - Reword the commit log
> V3->V4:
>  - No Changes
> V2->V3:
>  - No Changes
> V1->V2:
>  - Added clock and resets
>
>  arch/arm/boot/dts/qcom-ipq4019.dtsi | 44 +++++++++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> index b23591110bd2..5fa1af147df9 100644
> --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> @@ -38,6 +38,7 @@ aliases {
>                 spi1 = &blsp1_spi2;
>                 i2c0 = &blsp1_i2c3;
>                 i2c1 = &blsp1_i2c4;
> +               ethernet0 = &gmac;
>         };
>
>         cpus {
> @@ -591,6 +592,49 @@ wifi1: wifi@a800000 {
>                         status = "disabled";
>                 };
>
> +               gmac: ethernet@c080000 {
> +                       compatible = "qcom,ipq4019-ess-edma";
> +                       reg = <0xc080000 0x8000>;
> +                       resets = <&gcc ESS_RESET>;
> +                       reset-names = "ess";
> +                       clocks = <&gcc GCC_ESS_CLK>;
> +                       clock-names = "ess";
> +                       interrupts = <GIC_SPI  65 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI  66 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI  67 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI  68 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI  69 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI  70 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI  71 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI  72 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI  73 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI  74 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI  75 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI  76 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI  77 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI  78 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI  79 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI  80 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
> +                       phy-mode = "internal";
> +                       status = "disabled";

The fixed-link should be defined here AFAIK, otherwise it will fail probing with
just internal PHY mode.

Regards,
Robert
> +               };
> +
>                 mdio: mdio@90000 {
>                         #address-cells = <1>;
>                         #size-cells = <0>;
> --
> 2.37.3
>
Vladimir Oltean Nov. 4, 2022, 4:45 p.m. UTC | #7 
On Fri, Nov 04, 2022 at 05:42:30PM +0100, Robert Marko wrote:
> > +                       phy-mode = "internal";
> > +                       status = "disabled";
> 
> The fixed-link should be defined here AFAIK, otherwise it will fail probing with
> just internal PHY mode.

It wouldn't fail to probe because it has status = "disabled" by default,
and who enables that would also provide the fixed-link presumably.
But if the speed of the pseudo-MAC that goes to the switch is not board
specific, indeed the fixed-link belongs to the SoC dtsi.
Robert Marko Nov. 4, 2022, 4:50 p.m. UTC | #8 
On Fri, Nov 4, 2022 at 5:45 PM Vladimir Oltean <vladimir.oltean@nxp.com> wrote:
>
> On Fri, Nov 04, 2022 at 05:42:30PM +0100, Robert Marko wrote:
> > > +                       phy-mode = "internal";
> > > +                       status = "disabled";
> >
> > The fixed-link should be defined here AFAIK, otherwise it will fail probing with
> > just internal PHY mode.
>
> It wouldn't fail to probe because it has status = "disabled" by default,
> and who enables that would also provide the fixed-link presumably.
> But if the speed of the pseudo-MAC that goes to the switch is not board
> specific, indeed the fixed-link belongs to the SoC dtsi.

Yes, its directly connected to the switch CPU port and its a part of the SoC,
so it should be defined in the SoC DTSI as it cannot really be changed on
boards.

Regards,
Robert
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index b23591110bd2..5fa1af147df9 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -38,6 +38,7 @@  aliases {
 		spi1 = &blsp1_spi2;
 		i2c0 = &blsp1_i2c3;
 		i2c1 = &blsp1_i2c4;
+		ethernet0 = &gmac;
 	};
 
 	cpus {
@@ -591,6 +592,49 @@  wifi1: wifi@a800000 {
 			status = "disabled";
 		};
 
+		gmac: ethernet@c080000 {
+			compatible = "qcom,ipq4019-ess-edma";
+			reg = <0xc080000 0x8000>;
+			resets = <&gcc ESS_RESET>;
+			reset-names = "ess";
+			clocks = <&gcc GCC_ESS_CLK>;
+			clock-names = "ess";
+			interrupts = <GIC_SPI  65 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  66 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  67 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  68 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  69 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  70 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  71 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  72 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  73 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  74 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  75 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  76 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  77 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  78 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  79 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  80 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
+			phy-mode = "internal";
+			status = "disabled";
+		};
+
 		mdio: mdio@90000 {
 			#address-cells = <1>;
 			#size-cells = <0>;