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[v1] RISC-V: Fix some typo in vector-iterators.md

Message ID 20230605150753.2583349-1-pan2.li@intel.com
State Accepted
Headers
Series [v1] RISC-V: Fix some typo in vector-iterators.md |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Li, Pan2 via Gcc-patches June 5, 2023, 3:07 p.m. UTC 
  From: Pan Li <pan2.li@intel.com>

This patch would like to fix some typo in vector-iterators.md, aka:

[-"vnx1DI")-]{+"vnx1di")+}
[-"vnx2SI")-]{+"vnx2si")+}
[-"vnx1SI")-]{+"vnx1si")+}

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/vector-iterators.md: Fix typo in mode attr.
---
 gcc/config/riscv/vector-iterators.md | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Jeff Law June 5, 2023, 7 p.m. UTC | #1 
On 6/5/23 09:07, Pan Li via Gcc-patches wrote:
> From: Pan Li <pan2.li@intel.com>
> 
> This patch would like to fix some typo in vector-iterators.md, aka:
> 
> [-"vnx1DI")-]{+"vnx1di")+}
> [-"vnx2SI")-]{+"vnx2si")+}
> [-"vnx1SI")-]{+"vnx1si")+}
> 
> Signed-off-by: Pan Li <pan2.li@intel.com>
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/vector-iterators.md: Fix typo in mode attr.
OK
jeff
Li, Pan2 via Gcc-patches June 6, 2023, 1:15 a.m. UTC | #2 
Committed, thanks Jeff.

Pan

-----Original Message-----
From: Jeff Law <jeffreyalaw@gmail.com> 
Sent: Tuesday, June 6, 2023 3:01 AM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v1] RISC-V: Fix some typo in vector-iterators.md



On 6/5/23 09:07, Pan Li via Gcc-patches wrote:
> From: Pan Li <pan2.li@intel.com>
> 
> This patch would like to fix some typo in vector-iterators.md, aka:
> 
> [-"vnx1DI")-]{+"vnx1di")+}
> [-"vnx2SI")-]{+"vnx2si")+}
> [-"vnx1SI")-]{+"vnx1si")+}
> 
> Signed-off-by: Pan Li <pan2.li@intel.com>
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/vector-iterators.md: Fix typo in mode attr.
OK
jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index e4f2ba90799..665a77eaf50 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -1367,8 +1367,8 @@  (define_mode_attr vlmul1_zve64 [
   (VNx8HI "vnx4hi") (VNx16HI "vnx4hi") (VNx32HI "vnx4hi")
   (VNx1SI "vnx2si") (VNx2SI "vnx2si") (VNx4SI "vnx2si")
   (VNx8SI "vnx2si") (VNx16SI "vnx2si")
-  (VNx1DI "vnx1DI") (VNx2DI "vnx1DI")
-  (VNx4DI "vnx1DI") (VNx8DI "vnx1DI")
+  (VNx1DI "vnx1di") (VNx2DI "vnx1di")
+  (VNx4DI "vnx1di") (VNx8DI "vnx1di")
   (VNx1SF "vnx2sf") (VNx2SF "vnx2sf")
   (VNx4SF "vnx2sf") (VNx8SF "vnx2sf") (VNx16SF "vnx2sf")
   (VNx1DF "vnx1df") (VNx2DF "vnx1df")
@@ -1401,7 +1401,7 @@  (define_mode_attr vwlmul1_zve64 [
   (VNx1QI "vnx4hi") (VNx2QI "vnx4hi") (VNx4QI "vnx4hi")
   (VNx8QI "vnx4hi") (VNx16QI "vnx4hi") (VNx32QI "vnx4hi") (VNx64QI "vnx4hi")
   (VNx1HI "vnx2si") (VNx2HI "vnx2si") (VNx4HI "vnx2si")
-  (VNx8HI "vnx2si") (VNx16HI "vnx2si") (VNx32HI "vnx2SI")
+  (VNx8HI "vnx2si") (VNx16HI "vnx2si") (VNx32HI "vnx2si")
   (VNx1SI "vnx1di") (VNx2SI "vnx1di") (VNx4SI "vnx1di")
   (VNx8SI "vnx1di") (VNx16SI "vnx1di")
   (VNx1SF "vnx1df") (VNx2SF "vnx1df")
@@ -1412,7 +1412,7 @@  (define_mode_attr vwlmul1_zve32 [
   (VNx1QI "vnx2hi") (VNx2QI "vnx2hi") (VNx4QI "vnx2hi")
   (VNx8QI "vnx2hi") (VNx16QI "vnx2hi") (VNx32QI "vnx2hi")
   (VNx1HI "vnx1si") (VNx2HI "vnx1si") (VNx4HI "vnx1si")
-  (VNx8HI "vnx1si") (VNx16HI "vnx1SI")
+  (VNx8HI "vnx1si") (VNx16HI "vnx1si")
 ])
 
 (define_mode_attr VDEMOTE [