Message ID | 20230529162034.20481-5-alexandre.torgue@foss.st.com |
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State | New |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id v28-20020aa799dc000000b0064d3fb487cbsi177046pfi.72.2023.05.29.09.25.07; Mon, 29 May 2023 09:25:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=EMNMJVcC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229820AbjE2QVN (ORCPT <rfc822;callmefire3@gmail.com> + 99 others); Mon, 29 May 2023 12:21:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229792AbjE2QVI (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Mon, 29 May 2023 12:21:08 -0400 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43BF9B2; Mon, 29 May 2023 09:21:03 -0700 (PDT) Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34TBP5Lo014132; Mon, 29 May 2023 18:20:50 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=selector1; bh=/9ucJaTz4jZ8nYgc4TteZEetfep8vk7hqb+C2MB9aUw=; b=EMNMJVcCy7OjevTkkZpJ/LlKrYdk/tFU4rnfORJY52u7Xf1O4iXIRFj7qPMMOqUXn67I M/PGA9faiOG/20p7TulEumYyVbMJI6DOl/prUWUt8gedm2KOrD8RdxUakCtPZp9gzg99 aUzFmLBEM7kBN+vndyXbUcCZxtjDpMXfZ29UG3MwiAQYxeZEIanUbXEXCuglZc8AuaLE KcKXijMO0UFhH3Z1d+0HAONG0P+j2JsM4XPCVo1DXswK+WC8RbTnS447D90nQG5nFjIM p4GcQjaqfKnfzGr0qejBQJXLQfLADb6aecrMlpvS6LCMQH3Pv+owPY4lg5CfwQJYvDP4 0Q== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3quahy2mct-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 29 May 2023 18:20:50 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 08FA1100038; Mon, 29 May 2023 18:20:44 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id F35E6233C87; Mon, 29 May 2023 18:20:43 +0200 (CEST) Received: from localhost (10.201.21.93) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 29 May 2023 18:20:43 +0200 From: Alexandre Torgue <alexandre.torgue@foss.st.com> To: <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Linus Walleij <linus.walleij@linaro.org>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Arnd Bergmann <arnd@arndb.de>, Olof Johansson <olof@lixom.net>, <soc@kernel.org> CC: <linux-arm-kernel@lists.infradead.org>, <devicetree@vger.kernel.org>, Alexandre Torgue <alexandre.torgue@foss.st.com>, <linux-stm32@st-md-mailman.stormreply.com>, <linux-kernel@vger.kernel.org>, <linux-gpio@vger.kernel.org> Subject: [PATCH 04/11] dt-bindings: stm32: add st,stm32mp25 compatibles to the stm32 family Date: Mon, 29 May 2023 18:20:27 +0200 Message-ID: <20230529162034.20481-5-alexandre.torgue@foss.st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230529162034.20481-1-alexandre.torgue@foss.st.com> References: <20230529162034.20481-1-alexandre.torgue@foss.st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.201.21.93] X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-29_10,2023-05-29_01,2023-05-22_02 X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767246419210453728?= X-GMAIL-MSGID: =?utf-8?q?1767246419210453728?= |
Series |
Add STM32MP25 support
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Commit Message
Alexandre TORGUE
May 29, 2023, 4:20 p.m. UTC
STM32 family is extended by the addition of the STM32MP25 SoCs. It is composed
of 4 SoCs: STM32MP251, STM32MP253, STM32MP255 and STM32MP257.
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Comments
Hi Conor On 5/29/23 20:05, Conor Dooley wrote: > On Mon, May 29, 2023 at 06:20:27PM +0200, Alexandre Torgue wrote: >> STM32 family is extended by the addition of the STM32MP25 SoCs. It is composed >> of 4 SoCs: STM32MP251, STM32MP253, STM32MP255 and STM32MP257. >> >> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> >> >> diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml >> index 4af5b8f4f803..7d7ca33d2e61 100644 >> --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml >> +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml >> @@ -161,6 +161,15 @@ properties: >> - const: phytec,phycore-stm32mp157c-som >> - const: st,stm32mp157 >> >> + - items: >> + - const: st,stm32mp251 >> + - items: >> + - const: st,stm32mp253 >> + - items: >> + - const: st,stm32mp255 >> + - items: >> + - const: st,stm32mp257 > > I assume the slightly odd format is just to avoid churn when adding > the board compatibles. Yes, exactly. Alex > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > Thanks, > Conor. > >> + >> additionalProperties: true >> >> ... >> -- >> 2.17.1 >>
On 30/05/2023 10:39, Alexandre TORGUE wrote: > Hi Conor > > On 5/29/23 20:05, Conor Dooley wrote: >> On Mon, May 29, 2023 at 06:20:27PM +0200, Alexandre Torgue wrote: >>> STM32 family is extended by the addition of the STM32MP25 SoCs. It is composed >>> of 4 SoCs: STM32MP251, STM32MP253, STM32MP255 and STM32MP257. >>> >>> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> >>> >>> diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml >>> index 4af5b8f4f803..7d7ca33d2e61 100644 >>> --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml >>> +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml >>> @@ -161,6 +161,15 @@ properties: >>> - const: phytec,phycore-stm32mp157c-som >>> - const: st,stm32mp157 >>> >>> + - items: >>> + - const: st,stm32mp251 >>> + - items: >>> + - const: st,stm32mp253 >>> + - items: >>> + - const: st,stm32mp255 >>> + - items: >>> + - const: st,stm32mp257 >> >> I assume the slightly odd format is just to avoid churn when adding >> the board compatibles. > > Yes, exactly. > I don't get it. How are you going to extend it? Or rather - what are you documenting here? If these are SoCs, then this is not valid. We do not allow these alone. No, please drop it. Best regards, Krzysztof
Hi Krzysztof On 5/31/23 20:47, Krzysztof Kozlowski wrote: > On 30/05/2023 10:39, Alexandre TORGUE wrote: >> Hi Conor >> >> On 5/29/23 20:05, Conor Dooley wrote: >>> On Mon, May 29, 2023 at 06:20:27PM +0200, Alexandre Torgue wrote: >>>> STM32 family is extended by the addition of the STM32MP25 SoCs. It is composed >>>> of 4 SoCs: STM32MP251, STM32MP253, STM32MP255 and STM32MP257. >>>> >>>> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> >>>> >>>> diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml >>>> index 4af5b8f4f803..7d7ca33d2e61 100644 >>>> --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml >>>> +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml >>>> @@ -161,6 +161,15 @@ properties: >>>> - const: phytec,phycore-stm32mp157c-som >>>> - const: st,stm32mp157 >>>> >>>> + - items: >>>> + - const: st,stm32mp251 >>>> + - items: >>>> + - const: st,stm32mp253 >>>> + - items: >>>> + - const: st,stm32mp255 >>>> + - items: >>>> + - const: st,stm32mp257 >>> >>> I assume the slightly odd format is just to avoid churn when adding >>> the board compatibles. >> >> Yes, exactly. >> > > I don't get it. How are you going to extend it? Or rather - what are you > documenting here? If these are SoCs, then this is not valid. We do not > allow these alone. > > No, please drop it. Ok. I will drop it in V2 and update binding patch which defines the STM32 EV1 board. Thanks Alex > > Best regards, > Krzysztof >
On 30/05/2023 10:39, Alexandre TORGUE wrote: > Hi Conor > > On 5/29/23 20:05, Conor Dooley wrote: >> On Mon, May 29, 2023 at 06:20:27PM +0200, Alexandre Torgue wrote: >>> STM32 family is extended by the addition of the STM32MP25 SoCs. It is composed >>> of 4 SoCs: STM32MP251, STM32MP253, STM32MP255 and STM32MP257. >>> >>> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> >>> >>> diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml >>> index 4af5b8f4f803..7d7ca33d2e61 100644 >>> --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml >>> +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml >>> @@ -161,6 +161,15 @@ properties: >>> - const: phytec,phycore-stm32mp157c-som >>> - const: st,stm32mp157 >>> >>> + - items: >>> + - const: st,stm32mp251 >>> + - items: >>> + - const: st,stm32mp253 >>> + - items: >>> + - const: st,stm32mp255 >>> + - items: >>> + - const: st,stm32mp257 >> >> I assume the slightly odd format is just to avoid churn when adding >> the board compatibles. > > Yes, exactly. > I don't get it. How are you going to extend it? Or rather - what are you documenting here? If these are SoCs, then this is not valid. We do not allow these alone. No, please drop it. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 4af5b8f4f803..7d7ca33d2e61 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -161,6 +161,15 @@ properties: - const: phytec,phycore-stm32mp157c-som - const: st,stm32mp157 + - items: + - const: st,stm32mp251 + - items: + - const: st,stm32mp253 + - items: + - const: st,stm32mp255 + - items: + - const: st,stm32mp257 + additionalProperties: true ...