diff mbox series

RISC-V: Add __RISCV_ prefix to VXRM and FRM enum

Message ID 20230601231907.3879-1-juzhe.zhong@rivai.ai
State Unresolved
Headers
Series RISC-V: Add __RISCV_ prefix to VXRM and FRM enum |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

juzhe.zhong@rivai.ai June 1, 2023, 11:19 p.m. UTC 
  From: Juzhe-Zhong <juzhe.zhong@rivai.ai>

According to doc:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222/files
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/226

Add __RISCV_ prefix to VXRM and FRM enum.

gcc/ChangeLog:

        * config/riscv/riscv-vector-builtins.cc (DEF_RVV_VXRM_ENUM): Add __RISCV_ prefix.
        (DEF_RVV_FRM_ENUM): Ditto.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/frm-1.c: Ditto.
        * gcc.target/riscv/rvv/base/vxrm-1.c: Ditto.
        * gcc.target/riscv/rvv/base/vxrm-10.c: Ditto.
        * gcc.target/riscv/rvv/base/vxrm-11.c: Ditto.
        * gcc.target/riscv/rvv/base/vxrm-12.c: Ditto.
        * gcc.target/riscv/rvv/base/vxrm-6.c: Ditto.
        * gcc.target/riscv/rvv/base/vxrm-7.c: Ditto.
        * gcc.target/riscv/rvv/base/vxrm-8.c: Ditto.
        * gcc.target/riscv/rvv/base/vxrm-9.c: Ditto.

---
 gcc/config/riscv/riscv-vector-builtins.cc         |  8 ++++----
 gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c   | 10 +++++-----
 gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c  |  8 ++++----
 gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-10.c |  8 ++++----
 gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c |  4 ++--
 gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c |  4 ++--
 gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-6.c  |  4 ++--
 gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-7.c  |  4 ++--
 gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-8.c  |  4 ++--
 gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-9.c  |  8 ++++----
 10 files changed, 31 insertions(+), 31 deletions(-)

Comments

Jeff Law June 1, 2023, 11:49 p.m. UTC | #1 
On 6/1/23 17:19, juzhe.zhong@rivai.ai wrote:
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
> 
> According to doc:
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222/files
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/226
> 
> Add __RISCV_ prefix to VXRM and FRM enum.
> 
> gcc/ChangeLog:
> 
>          * config/riscv/riscv-vector-builtins.cc (DEF_RVV_VXRM_ENUM): Add __RISCV_ prefix.
>          (DEF_RVV_FRM_ENUM): Ditto.
> 
> gcc/testsuite/ChangeLog:
> 
>          * gcc.target/riscv/rvv/base/frm-1.c: Ditto.
>          * gcc.target/riscv/rvv/base/vxrm-1.c: Ditto.
>          * gcc.target/riscv/rvv/base/vxrm-10.c: Ditto.
>          * gcc.target/riscv/rvv/base/vxrm-11.c: Ditto.
>          * gcc.target/riscv/rvv/base/vxrm-12.c: Ditto.
>          * gcc.target/riscv/rvv/base/vxrm-6.c: Ditto.
>          * gcc.target/riscv/rvv/base/vxrm-7.c: Ditto.
>          * gcc.target/riscv/rvv/base/vxrm-8.c: Ditto.
>          * gcc.target/riscv/rvv/base/vxrm-9.c: Ditto.
OK
jeff
Li, Pan2 via Gcc-patches June 2, 2023, 1:09 a.m. UTC | #2 
Committed, thanks Jeff.

Pan

-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Jeff Law via Gcc-patches
Sent: Friday, June 2, 2023 7:49 AM
To: juzhe.zhong@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.cheng@sifive.com; palmer@rivosinc.com; rdapp.gcc@gmail.com
Subject: Re: [PATCH] RISC-V: Add __RISCV_ prefix to VXRM and FRM enum



On 6/1/23 17:19, juzhe.zhong@rivai.ai wrote:
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
> 
> According to doc:
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222/files
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/226
> 
> Add __RISCV_ prefix to VXRM and FRM enum.
> 
> gcc/ChangeLog:
> 
>          * config/riscv/riscv-vector-builtins.cc (DEF_RVV_VXRM_ENUM): Add __RISCV_ prefix.
>          (DEF_RVV_FRM_ENUM): Ditto.
> 
> gcc/testsuite/ChangeLog:
> 
>          * gcc.target/riscv/rvv/base/frm-1.c: Ditto.
>          * gcc.target/riscv/rvv/base/vxrm-1.c: Ditto.
>          * gcc.target/riscv/rvv/base/vxrm-10.c: Ditto.
>          * gcc.target/riscv/rvv/base/vxrm-11.c: Ditto.
>          * gcc.target/riscv/rvv/base/vxrm-12.c: Ditto.
>          * gcc.target/riscv/rvv/base/vxrm-6.c: Ditto.
>          * gcc.target/riscv/rvv/base/vxrm-7.c: Ditto.
>          * gcc.target/riscv/rvv/base/vxrm-8.c: Ditto.
>          * gcc.target/riscv/rvv/base/vxrm-9.c: Ditto.
OK
jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 43bf6d8f262..9e6dae98a6d 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -4026,11 +4026,11 @@  register_vxrm ()
 {
   auto_vec<string_int_pair, 4> values;
 #define DEF_RVV_VXRM_ENUM(NAME, VALUE)                                          \
-  values.quick_push (string_int_pair ("VXRM_" #NAME, VALUE));
+  values.quick_push (string_int_pair ("__RISCV_VXRM_" #NAME, VALUE));
 #include "riscv-vector-builtins.def"
 #undef DEF_RVV_VXRM_ENUM
 
-  lang_hooks.types.simulate_enum_decl (input_location, "RVV_VXRM", &values);
+  lang_hooks.types.simulate_enum_decl (input_location, "__RISCV_VXRM", &values);
 }
 
 /* Register the frm enum.  */
@@ -4039,11 +4039,11 @@  register_frm ()
 {
   auto_vec<string_int_pair, 5> values;
 #define DEF_RVV_FRM_ENUM(NAME, VALUE)                                          \
-  values.quick_push (string_int_pair ("FRM_" #NAME, VALUE));
+  values.quick_push (string_int_pair ("__RISCV_FRM_" #NAME, VALUE));
 #include "riscv-vector-builtins.def"
 #undef DEF_RVV_FRM_ENUM
 
-  lang_hooks.types.simulate_enum_decl (input_location, "RVV_FRM", &values);
+  lang_hooks.types.simulate_enum_decl (input_location, "__RISCV_FRM", &values);
 }
 
 /* Implement #pragma riscv intrinsic vector.  */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c
index f5635fb959e..ff19c8bc089 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c
@@ -5,27 +5,27 @@ 
 
 size_t f0 ()
 {
-  return FRM_RNE;
+  return __RISCV_FRM_RNE;
 }
 
 size_t f1 ()
 {
-  return FRM_RTZ;
+  return __RISCV_FRM_RTZ;
 }
 
 size_t f2 ()
 {
-  return FRM_RDN;
+  return __RISCV_FRM_RDN;
 }
 
 size_t f3 ()
 {
-  return FRM_RUP;
+  return __RISCV_FRM_RUP;
 }
 
 size_t f4 ()
 {
-  return FRM_RMM;
+  return __RISCV_FRM_RMM;
 }
 
 /* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*0} 1} } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c
index 0d364787ad0..b0ed27b0520 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c
@@ -5,22 +5,22 @@ 
 
 size_t f0 ()
 {
-  return VXRM_RNU;
+  return __RISCV_VXRM_RNU;
 }
 
 size_t f1 ()
 {
-  return VXRM_RNE;
+  return __RISCV_VXRM_RNE;
 }
 
 size_t f2 ()
 {
-  return VXRM_RDN;
+  return __RISCV_VXRM_RDN;
 }
 
 size_t f3 ()
 {
-  return VXRM_ROD;
+  return __RISCV_VXRM_ROD;
 }
 
 /* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*0} 1} } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-10.c
index a707aa1645e..3c7872bb73d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-10.c
@@ -8,16 +8,16 @@  void f (void * in, void *out, int32_t x, int n, int m)
   for (int i = 0; i < n; i++) {
     vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
     vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
-    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
-    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
+    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RDN, 4);
+    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4);
     __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
   }
   
   for (int i = 0; i < n; i++) {
     vint32m1_t v = __riscv_vle32_v_i32m1 (in + i + 1000, 4);
     vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i + 1000, 4);
-    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RNE, 4);
-    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RNE, 4);
+    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RNE, 4);
+    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RNE, 4);
     __riscv_vse32_v_i32m1 (out + 100 + i + 1000, v3, 4);
   }
 }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c
index 7f637a8b7f5..2cbd548eeb6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c
@@ -10,9 +10,9 @@  void f (void * in, void *out, int32_t x, int n, int m)
   for (int i = 0; i < n; i++) {
     vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
     vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
-    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
+    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RDN, 4);
     fn ();
-    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
+    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4);
     __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
   }
 }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c
index c3ab509f106..95a58ca6b90 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c
@@ -8,9 +8,9 @@  void f (void * in, void *out, int32_t x, int n, int m)
   for (int i = 0; i < n; i++) {
     vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
     vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
-    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
+    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RDN, 4);
     asm volatile ("csrwi\tvxrm,1");
-    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
+    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4);
     __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
   }
 }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-6.c
index 4b346d67c27..6ef469fdce8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-6.c
@@ -7,8 +7,8 @@  void f (void * in, void *out, int32_t x, int n, int m)
 {
   vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
   vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100, 4);
-  vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
-  v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
+  vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RDN, 4);
+  v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4);
   __riscv_vse32_v_i32m1 (out + 100, v3, 4);
 }
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-7.c
index 1ca795ce3f4..50902c37a55 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-7.c
@@ -7,8 +7,8 @@  void f (void * in, void *out, int32_t x, int n, int m)
 {
   vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
   vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100, 4);
-  vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RNE, 4);
-  v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
+  vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RNE, 4);
+  v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4);
   __riscv_vse32_v_i32m1 (out + 100, v3, 4);
 }
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-8.c
index 5799f731e21..3ed0d00d1e9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-8.c
@@ -8,8 +8,8 @@  void f (void * in, void *out, int32_t x, int n, int m)
   for (int i = 0; i < n; i++) {
     vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
     vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
-    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
-    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
+    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RDN, 4);
+    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4);
     __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
   }
 }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-9.c
index 13921d4af21..0939705b2e7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-9.c
@@ -8,16 +8,16 @@  void f (void * in, void *out, int32_t x, int n, int m)
   for (int i = 0; i < n; i++) {
     vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
     vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
-    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
-    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
+    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RDN, 4);
+    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4);
     __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
   }
   
   for (int i = 0; i < n; i++) {
     vint32m1_t v = __riscv_vle32_v_i32m1 (in + i + 1000, 4);
     vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i + 1000, 4);
-    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
-    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
+    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RDN, 4);
+    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4);
     __riscv_vse32_v_i32m1 (out + 100 + i + 1000, v3, 4);
   }
 }