diff mbox series

[v2,1/8] x86: KVM: Move existing x86 CPUID leaf [CPUID_7_1_EAX] to kvm-only leaf

Message ID 20221103025030.78371-2-jiaxi.chen@linux.intel.com
State New
Headers
Series x86: KVM: Advertise CPUID of new Intel platform instructions to user space |

Commit Message

Jiaxi Chen Nov. 3, 2022, 2:50 a.m. UTC 
  cpuid_leaf[12] CPUID_7_1_EAX has only two bits are in use currently:

 - AVX-VNNI CPUID.(EAX=7,ECX=1):EAX[bit 4]
 - AVX512-BF16 CPUID.(EAX=7,ECX=1):EAX[bit 5]

These two bits have no other kernel usages other than the guest
CPUID advertisement in KVM. Given that and to save space for kernel
feature bits, move these two bits to the kvm-only subleaves. The
existing leaf cpuid_leafs[12] is set to CPUID_DUMMY so future feature
can pick it. This basically reverts:

 - commit b85a0425d805 ("Enumerate AVX Vector Neural Network
instructions")
 - commit b302e4b176d0 ("x86/cpufeatures: Enumerate the new AVX512
BFLOAT16 instructions")
 - commit 1085a6b585d7 ("KVM: Expose AVX_VNNI instruction to guset")

Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com>
---
 arch/x86/include/asm/cpufeature.h  | 2 +-
 arch/x86/include/asm/cpufeatures.h | 4 ----
 arch/x86/kernel/cpu/common.c       | 6 ------
 arch/x86/kernel/cpu/cpuid-deps.c   | 1 -
 arch/x86/kvm/cpuid.c               | 2 +-
 arch/x86/kvm/reverse_cpuid.h       | 5 +++++
 6 files changed, 7 insertions(+), 13 deletions(-)

Comments

Borislav Petkov Nov. 3, 2022, 8:45 a.m. UTC | #1 
On Thu, Nov 03, 2022 at 10:50:23AM +0800, Jiaxi Chen wrote:
> diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
> index 1a85e1fb0922..fbb4e7bd2288 100644
> --- a/arch/x86/include/asm/cpufeature.h
> +++ b/arch/x86/include/asm/cpufeature.h
> @@ -24,7 +24,7 @@ enum cpuid_leafs
>  	CPUID_7_0_EBX,
>  	CPUID_D_1_EAX,
>  	CPUID_LNX_4,
> -	CPUID_7_1_EAX,
> +	CPUID_DUMMY,
>  	CPUID_8000_0008_EBX,
>  	CPUID_6_EAX,
>  	CPUID_8000_000A_EDX,

No, do this (diff ontop):

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index fbb4e7bd2288..b2905ddd7ab4 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -24,7 +24,7 @@ enum cpuid_leafs
 	CPUID_7_0_EBX,
 	CPUID_D_1_EAX,
 	CPUID_LNX_4,
-	CPUID_DUMMY,
+	CPUID_LNX_5,
 	CPUID_8000_0008_EBX,
 	CPUID_6_EAX,
 	CPUID_8000_000A_EDX,
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 91acf8b8e493..5c9023438e57 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -306,6 +306,8 @@
 #define X86_FEATURE_RSB_VMEXIT_LITE	(11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */
 #define X86_FEATURE_CALL_DEPTH		(11*32+18) /* "" Call depth tracking for RSB stuffing */
 
+/* Linux-defined mapping, word 12 */
+
 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
 #define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
 #define X86_FEATURE_IRPERF		(13*32+ 1) /* Instructions Retired Count */

---

I'm pretty sure we'll need new bits soon so let's reuse that one for
Linux-defined flags.

Then you can drop patch 2.

Thx.
Jiaxi Chen Nov. 4, 2022, 2:01 a.m. UTC | #2 
On 11/3/2022 4:45 PM, Borislav Petkov wrote:
> On Thu, Nov 03, 2022 at 10:50:23AM +0800, Jiaxi Chen wrote:
>> diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
>> index 1a85e1fb0922..fbb4e7bd2288 100644
>> --- a/arch/x86/include/asm/cpufeature.h
>> +++ b/arch/x86/include/asm/cpufeature.h
>> @@ -24,7 +24,7 @@ enum cpuid_leafs
>>  	CPUID_7_0_EBX,
>>  	CPUID_D_1_EAX,
>>  	CPUID_LNX_4,
>> -	CPUID_7_1_EAX,
>> +	CPUID_DUMMY,
>>  	CPUID_8000_0008_EBX,
>>  	CPUID_6_EAX,
>>  	CPUID_8000_000A_EDX,
> 
> No, do this (diff ontop):
> 
> diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
> index fbb4e7bd2288..b2905ddd7ab4 100644
> --- a/arch/x86/include/asm/cpufeature.h
> +++ b/arch/x86/include/asm/cpufeature.h
> @@ -24,7 +24,7 @@ enum cpuid_leafs
>  	CPUID_7_0_EBX,
>  	CPUID_D_1_EAX,
>  	CPUID_LNX_4,
> -	CPUID_DUMMY,
> +	CPUID_LNX_5,
>  	CPUID_8000_0008_EBX,
>  	CPUID_6_EAX,
>  	CPUID_8000_000A_EDX,
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 91acf8b8e493..5c9023438e57 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -306,6 +306,8 @@
>  #define X86_FEATURE_RSB_VMEXIT_LITE	(11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */
>  #define X86_FEATURE_CALL_DEPTH		(11*32+18) /* "" Call depth tracking for RSB stuffing */
>  
> +/* Linux-defined mapping, word 12 */
> +
>  /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
>  #define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
>  #define X86_FEATURE_IRPERF		(13*32+ 1) /* Instructions Retired Count */
> 
> ---
> 
> I'm pretty sure we'll need new bits soon so let's reuse that one for
> Linux-defined flags.
> 
> Then you can drop patch 2.
> 

Hi Boris,

Yes, that's reasonable. I understand the goodnees of putting CPUID_LNX_5
here is to avoid changing the array length [NCAPINTS] and other parts twice.
But before new bits come, word 12 is empty in this gap. Is that ok?
Borislav Petkov Nov. 4, 2022, 11:23 a.m. UTC | #3 
On Fri, Nov 04, 2022 at 10:01:55AM +0800, Jiaxi Chen wrote:
> But before new bits come, word 12 is empty in this gap. Is that ok?

Yes.
diff mbox series

Patch

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 1a85e1fb0922..fbb4e7bd2288 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -24,7 +24,7 @@  enum cpuid_leafs
 	CPUID_7_0_EBX,
 	CPUID_D_1_EAX,
 	CPUID_LNX_4,
-	CPUID_7_1_EAX,
+	CPUID_DUMMY,
 	CPUID_8000_0008_EBX,
 	CPUID_6_EAX,
 	CPUID_8000_000A_EDX,
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index ef4775c6db01..cabe96df9555 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -305,10 +305,6 @@ 
 #define X86_FEATURE_USE_IBPB_FW		(11*32+16) /* "" Use IBPB during runtime firmware calls */
 #define X86_FEATURE_RSB_VMEXIT_LITE	(11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */
 
-/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
-#define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */
-#define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
-
 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
 #define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
 #define X86_FEATURE_IRPERF		(13*32+ 1) /* Instructions Retired Count */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 3e508f239098..0c19c84d7ba0 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1026,12 +1026,6 @@  void get_cpu_cap(struct cpuinfo_x86 *c)
 		c->x86_capability[CPUID_7_0_EBX] = ebx;
 		c->x86_capability[CPUID_7_ECX] = ecx;
 		c->x86_capability[CPUID_7_EDX] = edx;
-
-		/* Check valid sub-leaf index before accessing it */
-		if (eax >= 1) {
-			cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);
-			c->x86_capability[CPUID_7_1_EAX] = eax;
-		}
 	}
 
 	/* Extended state features: level 0x0000000d */
diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c
index c881bcafba7d..a88e0e8c39fa 100644
--- a/arch/x86/kernel/cpu/cpuid-deps.c
+++ b/arch/x86/kernel/cpu/cpuid-deps.c
@@ -68,7 +68,6 @@  static const struct cpuid_dep cpuid_deps[] = {
 	{ X86_FEATURE_CQM_OCCUP_LLC,		X86_FEATURE_CQM_LLC   },
 	{ X86_FEATURE_CQM_MBM_TOTAL,		X86_FEATURE_CQM_LLC   },
 	{ X86_FEATURE_CQM_MBM_LOCAL,		X86_FEATURE_CQM_LLC   },
-	{ X86_FEATURE_AVX512_BF16,		X86_FEATURE_AVX512VL  },
 	{ X86_FEATURE_AVX512_FP16,		X86_FEATURE_AVX512BW  },
 	{ X86_FEATURE_ENQCMD,			X86_FEATURE_XSAVES    },
 	{ X86_FEATURE_PER_THREAD_MBA,		X86_FEATURE_MBA       },
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 7065462378e2..89f5e7f0402b 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -656,7 +656,7 @@  void kvm_set_cpu_caps(void)
 	if (boot_cpu_has(X86_FEATURE_AMD_SSBD))
 		kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
 
-	kvm_cpu_cap_mask(CPUID_7_1_EAX,
+	kvm_cpu_cap_init_scattered(CPUID_7_1_EAX,
 		F(AVX_VNNI) | F(AVX512_BF16)
 	);
 
diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h
index a19d473d0184..674de5b24f8d 100644
--- a/arch/x86/kvm/reverse_cpuid.h
+++ b/arch/x86/kvm/reverse_cpuid.h
@@ -13,6 +13,7 @@ 
  */
 enum kvm_only_cpuid_leafs {
 	CPUID_12_EAX	 = NCAPINTS,
+	CPUID_7_1_EAX,
 	NR_KVM_CPU_CAPS,
 
 	NKVMCAPINTS = NR_KVM_CPU_CAPS - NCAPINTS,
@@ -24,6 +25,10 @@  enum kvm_only_cpuid_leafs {
 #define KVM_X86_FEATURE_SGX1		KVM_X86_FEATURE(CPUID_12_EAX, 0)
 #define KVM_X86_FEATURE_SGX2		KVM_X86_FEATURE(CPUID_12_EAX, 1)
 
+/* Intel-defined sub-features, CPUID level 0x00000007:1 (EAX) */
+#define X86_FEATURE_AVX_VNNI            KVM_X86_FEATURE(CPUID_7_1_EAX, 4)
+#define X86_FEATURE_AVX512_BF16         KVM_X86_FEATURE(CPUID_7_1_EAX, 5)
+
 struct cpuid_reg {
 	u32 function;
 	u32 index;