Message ID | 20230512085321.13259-4-alexghiti@rivosinc.com |
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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id s7-20020a1cf207000000b003e91b9a92c9sm27963429wmc.24.2023.05.12.01.56.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 01:56:56 -0700 (PDT) From: Alexandre Ghiti <alexghiti@rivosinc.com> To: Jonathan Corbet <corbet@lwn.net>, Peter Zijlstra <peterz@infradead.org>, Ingo Molnar <mingo@redhat.com>, Arnaldo Carvalho de Melo <acme@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Alexander Shishkin <alexander.shishkin@linux.intel.com>, Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>, Ian Rogers <irogers@google.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Atish Patra <atishp@atishpatra.org>, Anup Patel <anup@brainfault.org>, Will Deacon <will@kernel.org>, Rob Herring <robh@kernel.org>, Andrew Jones <ajones@ventanamicro.com>, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Cc: Alexandre Ghiti <alexghiti@rivosinc.com> Subject: [PATCH v2 03/10] riscv: Make legacy counter enum match the HW numbering Date: Fri, 12 May 2023 10:53:14 +0200 Message-Id: <20230512085321.13259-4-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230512085321.13259-1-alexghiti@rivosinc.com> References: <20230512085321.13259-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765678434581182965?= X-GMAIL-MSGID: =?utf-8?q?1765678434581182965?= |
Series |
riscv: Allow userspace to directly access perf counters
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Commit Message
Alexandre Ghiti
May 12, 2023, 8:53 a.m. UTC
RISCV_PMU_LEGACY_INSTRET used to be set to 1 whereas the offset of this
hardware counter from CSR_CYCLE is actually 2: make this offset match the
real hw offset so that we can directly expose those values to userspace.
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
---
drivers/perf/riscv_pmu_legacy.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
Comments
On Fri, May 12, 2023 at 10:53:14AM +0200, Alexandre Ghiti wrote: > RISCV_PMU_LEGACY_INSTRET used to be set to 1 whereas the offset of this > hardware counter from CSR_CYCLE is actually 2: make this offset match the > real hw offset so that we can directly expose those values to userspace. > > Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> > --- > drivers/perf/riscv_pmu_legacy.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legacy.c > index ca9e20bfc7ac..0d8c9d8849ee 100644 > --- a/drivers/perf/riscv_pmu_legacy.c > +++ b/drivers/perf/riscv_pmu_legacy.c > @@ -12,8 +12,11 @@ > #include <linux/perf/riscv_pmu.h> > #include <linux/platform_device.h> > > -#define RISCV_PMU_LEGACY_CYCLE 0 > -#define RISCV_PMU_LEGACY_INSTRET 1 > +enum { > + RISCV_PMU_LEGACY_CYCLE, > + RISCV_PMU_LEGACY_TIME, > + RISCV_PMU_LEGACY_INSTRET > +}; I guess this doesn't hurt, since these are just indices internal to this driver, but it's a bit odd to also have a RISCV_PMU_LEGACY_TIME, when the driver is only for cycle and instret, as its Kconfig help text says. Thanks, drew
On 31/05/2023 16:01, Andrew Jones wrote: > On Fri, May 12, 2023 at 10:53:14AM +0200, Alexandre Ghiti wrote: >> RISCV_PMU_LEGACY_INSTRET used to be set to 1 whereas the offset of this >> hardware counter from CSR_CYCLE is actually 2: make this offset match the >> real hw offset so that we can directly expose those values to userspace. >> >> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> >> --- >> drivers/perf/riscv_pmu_legacy.c | 7 +++++-- >> 1 file changed, 5 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legacy.c >> index ca9e20bfc7ac..0d8c9d8849ee 100644 >> --- a/drivers/perf/riscv_pmu_legacy.c >> +++ b/drivers/perf/riscv_pmu_legacy.c >> @@ -12,8 +12,11 @@ >> #include <linux/perf/riscv_pmu.h> >> #include <linux/platform_device.h> >> >> -#define RISCV_PMU_LEGACY_CYCLE 0 >> -#define RISCV_PMU_LEGACY_INSTRET 1 >> +enum { >> + RISCV_PMU_LEGACY_CYCLE, >> + RISCV_PMU_LEGACY_TIME, >> + RISCV_PMU_LEGACY_INSTRET >> +}; > I guess this doesn't hurt, since these are just indices internal to this > driver, but it's a bit odd to also have a RISCV_PMU_LEGACY_TIME, when > the driver is only for cycle and instret, as its Kconfig help text says. I understand and you're right, that's weird, so I'll change that with the following: diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legacy.c index ca9e20bfc7ac..6a000abc28bb 100644 --- a/drivers/perf/riscv_pmu_legacy.c +++ b/drivers/perf/riscv_pmu_legacy.c @@ -13,7 +13,7 @@ #include <linux/platform_device.h> #define RISCV_PMU_LEGACY_CYCLE 0 -#define RISCV_PMU_LEGACY_INSTRET 1 +#define RISCV_PMU_LEGACY_INSTRET 2 static bool pmu_init_done; Thanks! > Thanks, > drew > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legacy.c index ca9e20bfc7ac..0d8c9d8849ee 100644 --- a/drivers/perf/riscv_pmu_legacy.c +++ b/drivers/perf/riscv_pmu_legacy.c @@ -12,8 +12,11 @@ #include <linux/perf/riscv_pmu.h> #include <linux/platform_device.h> -#define RISCV_PMU_LEGACY_CYCLE 0 -#define RISCV_PMU_LEGACY_INSTRET 1 +enum { + RISCV_PMU_LEGACY_CYCLE, + RISCV_PMU_LEGACY_TIME, + RISCV_PMU_LEGACY_INSTRET +}; static bool pmu_init_done;