diff mbox series

RISC-V: Remove FRM for vfwcvt (RVV float to float widening conversion)

Message ID 20230531103510.211726-1-juzhe.zhong@rivai.ai
State Repeat Merge
Headers
Series RISC-V: Remove FRM for vfwcvt (RVV float to float widening conversion) |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

juzhe.zhong@rivai.ai May 31, 2023, 10:35 a.m. UTC 
  From: Juzhe-Zhong <juzhe.zhong@rivai.ai>

Base on the discussion here:
https://github.com/riscv/riscv-v-spec/issues/884

vfwcvt doesn't depend on FRM. So remove FRM preparing for mode switching support.

gcc/ChangeLog:

        * config/riscv/vector.md: Remove FRM.

---
 gcc/config/riscv/vector.md | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

Comments

Jeff Law May 31, 2023, 1:03 p.m. UTC | #1 
On 5/31/23 04:35, juzhe.zhong@rivai.ai wrote:
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
> 
> Base on the discussion here:
> https://github.com/riscv/riscv-v-spec/issues/884
> 
> vfwcvt doesn't depend on FRM. So remove FRM preparing for mode switching support.
> 
> gcc/ChangeLog:
> 
>          * config/riscv/vector.md: Remove FRM.
OK
jeff
Li, Pan2 via Gcc-patches May 31, 2023, 1:54 p.m. UTC | #2 
Committed, thanks Jeff.

Pan

-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Jeff Law via Gcc-patches
Sent: Wednesday, May 31, 2023 9:03 PM
To: juzhe.zhong@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com; kito.cheng@sifive.com; palmer@dabbelt.com; palmer@rivosinc.com; rdapp.gcc@gmail.com
Subject: Re: [PATCH] RISC-V: Remove FRM for vfwcvt (RVV float to float widening conversion)



On 5/31/23 04:35, juzhe.zhong@rivai.ai wrote:
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
> 
> Base on the discussion here:
> https://github.com/riscv/riscv-v-spec/issues/884
> 
> vfwcvt doesn't depend on FRM. So remove FRM preparing for mode switching support.
> 
> gcc/ChangeLog:
> 
>          * config/riscv/vector.md: Remove FRM.
OK
jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index cd696da5d89..28e7e63ce69 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7180,10 +7180,8 @@ 
 	     (match_operand 5 "const_int_operand"                 "    i,    i")
 	     (match_operand 6 "const_int_operand"                 "    i,    i")
 	     (match_operand 7 "const_int_operand"                 "    i,    i")
-	     (match_operand 8 "const_int_operand"                 "    i,    i")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)
-	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (float_extend:VWEXTF
 	     (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr,   vr"))
 	  (match_operand:VWEXTF 2 "vector_merge_operand"          "   vu,    0")))]