diff mbox series

RISC-V: Add ZVFH extension to the -march= option

Message ID 20230531065806.1822850-1-pan2.li@intel.com
State Unresolved
Headers
Series RISC-V: Add ZVFH extension to the -march= option |

Checks

Context Check Description
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Commit Message

Li, Pan2 via Gcc-patches May 31, 2023, 6:58 a.m. UTC 
  From: Pan Li <pan2.li@intel.com>

This patch would like to add new sub extension (aka ZVFH) to the -march= option.
To make it simple, only the sub extension itself is involved in this patch, and
the underlying FP16 related RVV intrinsic API depends on the TARGET_ZVFH.

The Zvfh extension depends on the Zve32f and Zfhmin extensions. You can locate
more information about ZVFH from below spec doc.

https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#185-zvfh-vector-extension-for-half-precision-floating-point

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc:
	(riscv_implied_info): Add zvfh item.
	(riscv_ext_version_table): Ditto.
	(riscv_ext_flag_table): Ditto.
	* config/riscv/riscv-opts.h (MASK_ZVFH): New macro.
	(TARGET_ZVFH): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/arch-21.c: New test.
	* gcc.target/riscv/predef-27.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc    |  4 ++
 gcc/config/riscv/riscv-opts.h              |  2 +
 gcc/testsuite/gcc.target/riscv/arch-21.c   |  5 ++
 gcc/testsuite/gcc.target/riscv/predef-27.c | 55 ++++++++++++++++++++++
 4 files changed, 66 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-21.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-27.c

Comments

Kito Cheng May 31, 2023, 7:06 a.m. UTC | #1 
LGTM

On Wed, May 31, 2023 at 2:58 PM <pan2.li@intel.com> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to add new sub extension (aka ZVFH) to the -march= option.
> To make it simple, only the sub extension itself is involved in this patch, and
> the underlying FP16 related RVV intrinsic API depends on the TARGET_ZVFH.
>
> The Zvfh extension depends on the Zve32f and Zfhmin extensions. You can locate
> more information about ZVFH from below spec doc.
>
> https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#185-zvfh-vector-extension-for-half-precision-floating-point
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
>         * common/config/riscv/riscv-common.cc:
>         (riscv_implied_info): Add zvfh item.
>         (riscv_ext_version_table): Ditto.
>         (riscv_ext_flag_table): Ditto.
>         * config/riscv/riscv-opts.h (MASK_ZVFH): New macro.
>         (TARGET_ZVFH): Ditto.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/arch-21.c: New test.
>         * gcc.target/riscv/predef-27.c: New test.
> ---
>  gcc/common/config/riscv/riscv-common.cc    |  4 ++
>  gcc/config/riscv/riscv-opts.h              |  2 +
>  gcc/testsuite/gcc.target/riscv/arch-21.c   |  5 ++
>  gcc/testsuite/gcc.target/riscv/predef-27.c | 55 ++++++++++++++++++++++
>  4 files changed, 66 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-21.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/predef-27.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> index 92edafb516d..e6ed3df9ea6 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -105,6 +105,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
>    {"zfh", "zfhmin"},
>    {"zfhmin", "f"},
>    {"zvfhmin", "zve32f"},
> +  {"zvfh", "zve32f"},
> +  {"zvfh", "zfhmin"},
>
>    {"zhinx", "zhinxmin"},
>    {"zhinxmin", "zfinx"},
> @@ -218,6 +220,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
>    {"zfh",       ISA_SPEC_CLASS_NONE, 1, 0},
>    {"zfhmin",    ISA_SPEC_CLASS_NONE, 1, 0},
>    {"zvfhmin",   ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zvfh",      ISA_SPEC_CLASS_NONE, 1, 0},
>
>    {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
>
> @@ -1262,6 +1265,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
>    {"zfhmin",    &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
>    {"zfh",       &gcc_options::x_riscv_zf_subext, MASK_ZFH},
>    {"zvfhmin",   &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
> +  {"zvfh",      &gcc_options::x_riscv_zf_subext, MASK_ZVFH},
>
>    {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
>
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index f34ca993689..5f387d0e393 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -201,10 +201,12 @@ enum riscv_entity
>  #define MASK_ZFHMIN   (1 << 0)
>  #define MASK_ZFH      (1 << 1)
>  #define MASK_ZVFHMIN  (1 << 2)
> +#define MASK_ZVFH     (1 << 3)
>
>  #define TARGET_ZFHMIN  ((riscv_zf_subext & MASK_ZFHMIN) != 0)
>  #define TARGET_ZFH     ((riscv_zf_subext & MASK_ZFH) != 0)
>  #define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
> +#define TARGET_ZVFH    ((riscv_zf_subext & MASK_ZVFH) != 0)
>
>  #define MASK_ZMMUL      (1 << 0)
>  #define TARGET_ZMMUL    ((riscv_zm_subext & MASK_ZMMUL) != 0)
> diff --git a/gcc/testsuite/gcc.target/riscv/arch-21.c b/gcc/testsuite/gcc.target/riscv/arch-21.c
> new file mode 100644
> index 00000000000..8a239a9255c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/arch-21.c
> @@ -0,0 +1,5 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=rv32gcv_zvfh -mabi=ilp32 -mcmodel=medlow" } */
> +int foo()
> +{
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/predef-27.c b/gcc/testsuite/gcc.target/riscv/predef-27.c
> new file mode 100644
> index 00000000000..0f9ab4417a6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/predef-27.c
> @@ -0,0 +1,55 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=rv64i_zvfh -mabi=lp64f -mcmodel=medlow -misa-spec=20191213" } */
> +
> +int main () {
> +
> +#ifndef __riscv_arch_test
> +#error "__riscv_arch_test"
> +#endif
> +
> +#if __riscv_xlen != 64
> +#error "__riscv_xlen"
> +#endif
> +
> +#if !defined(__riscv_i)
> +#error "__riscv_i"
> +#endif
> +
> +#if !defined(__riscv_f)
> +#error "__riscv_f"
> +#endif
> +
> +#if !defined(__riscv_zvfh)
> +#error "__riscv_zvfh"
> +#endif
> +
> +#if !defined(__riscv_zfhmin)
> +#error "__riscv_zfhmin"
> +#endif
> +
> +#if defined(__riscv_zvfhmin)
> +#error "__riscv_zvfhmin"
> +#endif
> +
> +#if defined(__riscv_v)
> +#error "__riscv_v"
> +#endif
> +
> +#if defined(__riscv_d)
> +#error "__riscv_d"
> +#endif
> +
> +#if defined(__riscv_c)
> +#error "__riscv_c"
> +#endif
> +
> +#if defined(__riscv_a)
> +#error "__riscv_a"
> +#endif
> +
> +#if defined(__riscv_zfh)
> +#error "__riscv_zfh"
> +#endif
> +
> +  return 0;
> +}
> --
> 2.34.1
>
Li, Pan2 via Gcc-patches May 31, 2023, 7:27 a.m. UTC | #2 
Committed, thanks Kito.

Pan

-----Original Message-----
From: Kito Cheng <kito.cheng@sifive.com> 
Sent: Wednesday, May 31, 2023 3:06 PM
To: Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH] RISC-V: Add ZVFH extension to the -march= option

LGTM

On Wed, May 31, 2023 at 2:58 PM <pan2.li@intel.com> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to add new sub extension (aka ZVFH) to the -march= option.
> To make it simple, only the sub extension itself is involved in this 
> patch, and the underlying FP16 related RVV intrinsic API depends on the TARGET_ZVFH.
>
> The Zvfh extension depends on the Zve32f and Zfhmin extensions. You 
> can locate more information about ZVFH from below spec doc.
>
> https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#185-zvfh
> -vector-extension-for-half-precision-floating-point
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
>         * common/config/riscv/riscv-common.cc:
>         (riscv_implied_info): Add zvfh item.
>         (riscv_ext_version_table): Ditto.
>         (riscv_ext_flag_table): Ditto.
>         * config/riscv/riscv-opts.h (MASK_ZVFH): New macro.
>         (TARGET_ZVFH): Ditto.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/arch-21.c: New test.
>         * gcc.target/riscv/predef-27.c: New test.
> ---
>  gcc/common/config/riscv/riscv-common.cc    |  4 ++
>  gcc/config/riscv/riscv-opts.h              |  2 +
>  gcc/testsuite/gcc.target/riscv/arch-21.c   |  5 ++
>  gcc/testsuite/gcc.target/riscv/predef-27.c | 55 
> ++++++++++++++++++++++
>  4 files changed, 66 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-21.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/predef-27.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index 92edafb516d..e6ed3df9ea6 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -105,6 +105,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
>    {"zfh", "zfhmin"},
>    {"zfhmin", "f"},
>    {"zvfhmin", "zve32f"},
> +  {"zvfh", "zve32f"},
> +  {"zvfh", "zfhmin"},
>
>    {"zhinx", "zhinxmin"},
>    {"zhinxmin", "zfinx"},
> @@ -218,6 +220,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
>    {"zfh",       ISA_SPEC_CLASS_NONE, 1, 0},
>    {"zfhmin",    ISA_SPEC_CLASS_NONE, 1, 0},
>    {"zvfhmin",   ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zvfh",      ISA_SPEC_CLASS_NONE, 1, 0},
>
>    {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
>
> @@ -1262,6 +1265,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
>    {"zfhmin",    &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
>    {"zfh",       &gcc_options::x_riscv_zf_subext, MASK_ZFH},
>    {"zvfhmin",   &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
> +  {"zvfh",      &gcc_options::x_riscv_zf_subext, MASK_ZVFH},
>
>    {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
>
> diff --git a/gcc/config/riscv/riscv-opts.h 
> b/gcc/config/riscv/riscv-opts.h index f34ca993689..5f387d0e393 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -201,10 +201,12 @@ enum riscv_entity
>  #define MASK_ZFHMIN   (1 << 0)
>  #define MASK_ZFH      (1 << 1)
>  #define MASK_ZVFHMIN  (1 << 2)
> +#define MASK_ZVFH     (1 << 3)
>
>  #define TARGET_ZFHMIN  ((riscv_zf_subext & MASK_ZFHMIN) != 0)
>  #define TARGET_ZFH     ((riscv_zf_subext & MASK_ZFH) != 0)
>  #define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
> +#define TARGET_ZVFH    ((riscv_zf_subext & MASK_ZVFH) != 0)
>
>  #define MASK_ZMMUL      (1 << 0)
>  #define TARGET_ZMMUL    ((riscv_zm_subext & MASK_ZMMUL) != 0)
> diff --git a/gcc/testsuite/gcc.target/riscv/arch-21.c 
> b/gcc/testsuite/gcc.target/riscv/arch-21.c
> new file mode 100644
> index 00000000000..8a239a9255c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/arch-21.c
> @@ -0,0 +1,5 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=rv32gcv_zvfh -mabi=ilp32 -mcmodel=medlow" 
> +} */ int foo() { }
> diff --git a/gcc/testsuite/gcc.target/riscv/predef-27.c 
> b/gcc/testsuite/gcc.target/riscv/predef-27.c
> new file mode 100644
> index 00000000000..0f9ab4417a6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/predef-27.c
> @@ -0,0 +1,55 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=rv64i_zvfh -mabi=lp64f -mcmodel=medlow 
> +-misa-spec=20191213" } */
> +
> +int main () {
> +
> +#ifndef __riscv_arch_test
> +#error "__riscv_arch_test"
> +#endif
> +
> +#if __riscv_xlen != 64
> +#error "__riscv_xlen"
> +#endif
> +
> +#if !defined(__riscv_i)
> +#error "__riscv_i"
> +#endif
> +
> +#if !defined(__riscv_f)
> +#error "__riscv_f"
> +#endif
> +
> +#if !defined(__riscv_zvfh)
> +#error "__riscv_zvfh"
> +#endif
> +
> +#if !defined(__riscv_zfhmin)
> +#error "__riscv_zfhmin"
> +#endif
> +
> +#if defined(__riscv_zvfhmin)
> +#error "__riscv_zvfhmin"
> +#endif
> +
> +#if defined(__riscv_v)
> +#error "__riscv_v"
> +#endif
> +
> +#if defined(__riscv_d)
> +#error "__riscv_d"
> +#endif
> +
> +#if defined(__riscv_c)
> +#error "__riscv_c"
> +#endif
> +
> +#if defined(__riscv_a)
> +#error "__riscv_a"
> +#endif
> +
> +#if defined(__riscv_zfh)
> +#error "__riscv_zfh"
> +#endif
> +
> +  return 0;
> +}
> --
> 2.34.1
>
diff mbox series

Patch

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 92edafb516d..e6ed3df9ea6 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -105,6 +105,8 @@  static const riscv_implied_info_t riscv_implied_info[] =
   {"zfh", "zfhmin"},
   {"zfhmin", "f"},
   {"zvfhmin", "zve32f"},
+  {"zvfh", "zve32f"},
+  {"zvfh", "zfhmin"},
 
   {"zhinx", "zhinxmin"},
   {"zhinxmin", "zfinx"},
@@ -218,6 +220,7 @@  static const struct riscv_ext_version riscv_ext_version_table[] =
   {"zfh",       ISA_SPEC_CLASS_NONE, 1, 0},
   {"zfhmin",    ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvfhmin",   ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zvfh",      ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
 
@@ -1262,6 +1265,7 @@  static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"zfhmin",    &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
   {"zfh",       &gcc_options::x_riscv_zf_subext, MASK_ZFH},
   {"zvfhmin",   &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
+  {"zvfh",      &gcc_options::x_riscv_zf_subext, MASK_ZVFH},
 
   {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index f34ca993689..5f387d0e393 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -201,10 +201,12 @@  enum riscv_entity
 #define MASK_ZFHMIN   (1 << 0)
 #define MASK_ZFH      (1 << 1)
 #define MASK_ZVFHMIN  (1 << 2)
+#define MASK_ZVFH     (1 << 3)
 
 #define TARGET_ZFHMIN  ((riscv_zf_subext & MASK_ZFHMIN) != 0)
 #define TARGET_ZFH     ((riscv_zf_subext & MASK_ZFH) != 0)
 #define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
+#define TARGET_ZVFH    ((riscv_zf_subext & MASK_ZVFH) != 0)
 
 #define MASK_ZMMUL      (1 << 0)
 #define TARGET_ZMMUL    ((riscv_zm_subext & MASK_ZMMUL) != 0)
diff --git a/gcc/testsuite/gcc.target/riscv/arch-21.c b/gcc/testsuite/gcc.target/riscv/arch-21.c
new file mode 100644
index 00000000000..8a239a9255c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-21.c
@@ -0,0 +1,5 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gcv_zvfh -mabi=ilp32 -mcmodel=medlow" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-27.c b/gcc/testsuite/gcc.target/riscv/predef-27.c
new file mode 100644
index 00000000000..0f9ab4417a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-27.c
@@ -0,0 +1,55 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64i_zvfh -mabi=lp64f -mcmodel=medlow -misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_f)
+#error "__riscv_f"
+#endif
+
+#if !defined(__riscv_zvfh)
+#error "__riscv_zvfh"
+#endif
+
+#if !defined(__riscv_zfhmin)
+#error "__riscv_zfhmin"
+#endif
+
+#if defined(__riscv_zvfhmin)
+#error "__riscv_zvfhmin"
+#endif
+
+#if defined(__riscv_v)
+#error "__riscv_v"
+#endif
+
+#if defined(__riscv_d)
+#error "__riscv_d"
+#endif
+
+#if defined(__riscv_c)
+#error "__riscv_c"
+#endif
+
+#if defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+#if defined(__riscv_zfh)
+#error "__riscv_zfh"
+#endif
+
+  return 0;
+}