Message ID | 20230526062529.46747-3-william.qiu@starfivetech.com |
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State | New |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id x11-20020a17090a8a8b00b0023def94be5esi3276642pjn.20.2023.05.25.23.32.17; Thu, 25 May 2023 23:32:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242181AbjEZGZu convert rfc822-to-8bit (ORCPT <rfc822;zhanglyra.2023@gmail.com> + 99 others); Fri, 26 May 2023 02:25:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242143AbjEZGZm (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Fri, 26 May 2023 02:25:42 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13E9413D; Thu, 25 May 2023 23:25:38 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 4F5AC24E1BE; Fri, 26 May 2023 14:25:32 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 26 May 2023 14:25:32 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 26 May 2023 14:25:31 +0800 From: William Qiu <william.qiu@starfivetech.com> To: <devicetree@vger.kernel.org>, <linux-spi@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org> CC: Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Emil Renner Berthing <kernel@esmil.dk>, Ziv Xu <ziv.xu@starfivetech.com>, William Qiu <william.qiu@starfivetech.com> Subject: [PATCH v1 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI Date: Fri, 26 May 2023 14:25:28 +0800 Message-ID: <20230526062529.46747-3-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230526062529.46747-1-william.qiu@starfivetech.com> References: <20230526062529.46747-1-william.qiu@starfivetech.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766937329835675460?= X-GMAIL-MSGID: =?utf-8?q?1766937329835675460?= |
Series |
Add initialization of clock for StarFive JH7110 SoC
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Commit Message
William Qiu
May 26, 2023, 6:25 a.m. UTC
Add QSPI clock operation in device probe. Signed-off-by: William Qiu <william.qiu@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> --- drivers/spi/spi-cadence-quadspi.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)
Comments
On Fri, May 26, 2023 at 02:25:28PM +0800, William Qiu wrote: > if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { > + qspi_ahb = devm_clk_get(dev, "qspi-ahb"); > + if (IS_ERR(qspi_ahb)) { > + dev_err(dev, "Cannot claim QSPI_AHB clock.\n"); > + ret = PTR_ERR(qspi_ahb); > + return ret; > + } > + > + ret = clk_prepare_enable(qspi_ahb); > + if (ret) { > + dev_err(dev, "Cannot enable QSPI AHB clock.\n"); > + goto probe_clk_failed; > + } Nothing ever disables or unprepares this clock as far as I can tell? Perhaps also consider using the clk_bulk_ APIs.
On 2023/5/26 23:36, Mark Brown wrote: > On Fri, May 26, 2023 at 02:25:28PM +0800, William Qiu wrote: > >> if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { >> + qspi_ahb = devm_clk_get(dev, "qspi-ahb"); >> + if (IS_ERR(qspi_ahb)) { >> + dev_err(dev, "Cannot claim QSPI_AHB clock.\n"); >> + ret = PTR_ERR(qspi_ahb); >> + return ret; >> + } >> + >> + ret = clk_prepare_enable(qspi_ahb); >> + if (ret) { >> + dev_err(dev, "Cannot enable QSPI AHB clock.\n"); >> + goto probe_clk_failed; >> + } > > Nothing ever disables or unprepares this clock as far as I can tell? > Perhaps also consider using the clk_bulk_ APIs. I will add in next version. Thanks for taking time to review this patch series and give useful suggestions. Best regards, William
On 2023/5/29 14:44, William Qiu wrote: > > > On 2023/5/26 23:36, Mark Brown wrote: >> On Fri, May 26, 2023 at 02:25:28PM +0800, William Qiu wrote: >> >>> if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { >>> + qspi_ahb = devm_clk_get(dev, "qspi-ahb"); >>> + if (IS_ERR(qspi_ahb)) { >>> + dev_err(dev, "Cannot claim QSPI_AHB clock.\n"); >>> + ret = PTR_ERR(qspi_ahb); >>> + return ret; >>> + } >>> + >>> + ret = clk_prepare_enable(qspi_ahb); >>> + if (ret) { >>> + dev_err(dev, "Cannot enable QSPI AHB clock.\n"); >>> + goto probe_clk_failed; >>> + } >> >> Nothing ever disables or unprepares this clock as far as I can tell? >> Perhaps also consider using the clk_bulk_ APIs. > > I will add in next version. > > Thanks for taking time to review this patch series and give useful > suggestions. > > Best regards, > William Hi Mark, Now I want to replace the original devm_clk_get API in the driver with devm_clk_bulk_get_all API, which can achieve compatibility, but it seems that it is not good for other ip with only one clock, so I want to ask about that can I replace it? Or define that inside jh7110? Best regards, William
On Tue, May 30, 2023 at 10:05:38AM +0800, William Qiu wrote: > On 2023/5/29 14:44, William Qiu wrote: > > On 2023/5/26 23:36, Mark Brown wrote: > >> Nothing ever disables or unprepares this clock as far as I can tell? > >> Perhaps also consider using the clk_bulk_ APIs. > > I will add in next version. > Now I want to replace the original devm_clk_get API in the > driver with devm_clk_bulk_get_all API, which can achieve compatibility, > but it seems that it is not good for other ip with only one clock, so I > want to ask about that can I replace it? Or define that inside jh7110? You could always specify a different array of clocks depending on which compatible the driver sees, just like you'd conditionally request clocks individually.
On 2023/5/30 18:33, Mark Brown wrote: > On Tue, May 30, 2023 at 10:05:38AM +0800, William Qiu wrote: >> On 2023/5/29 14:44, William Qiu wrote: >> > On 2023/5/26 23:36, Mark Brown wrote: > >> >> Nothing ever disables or unprepares this clock as far as I can tell? >> >> Perhaps also consider using the clk_bulk_ APIs. > >> > I will add in next version. > >> Now I want to replace the original devm_clk_get API in the >> driver with devm_clk_bulk_get_all API, which can achieve compatibility, >> but it seems that it is not good for other ip with only one clock, so I >> want to ask about that can I replace it? Or define that inside jh7110? > > You could always specify a different array of clocks depending on which > compatible the driver sees, just like you'd conditionally request clocks > individually. Hi Mark, If specify a different array of clocks depending on which compatible the driver sees, since there will also be clock operations in the suspend and resume interfaces, this can make the code look complicated. My thoughts are as follows: Modify the following code 1658 /* Obtain QSPI clock. */ 1659 cqspi->clk = devm_clk_get(dev, NULL); 1660 if (IS_ERR(cqspi->clk)) { 1661 dev_err(dev, "Cannot claim QSPI clock.\n"); 1662 ret = PTR_ERR(cqspi->clk); 1663 return ret; 1664 } as following: /* Obtain QSPI clock. */ cqspi->num_clks = devm_clk_bulk_get_all(dev, &cqspi->clks); if (cqspi->num_clks < 0) { dev_err(dev, "Cannot claim QSPI clock: %u\n", cqspi->num_clks); return -EINVAL; } This way, the code will look simpler and clearer. How do you think about it. Best Regards, William
On Wed, May 31, 2023 at 02:19:16PM +0800, William Qiu wrote: > On 2023/5/30 18:33, Mark Brown wrote: > > You could always specify a different array of clocks depending on which > > compatible the driver sees, just like you'd conditionally request clocks > > individually. > If specify a different array of clocks depending on which compatible > the driver sees, since there will also be clock operations in the suspend > and resume interfaces, this can make the code look complicated. If you store the clock count and array in the driver data that should be fairly simple I think. > as following: > /* Obtain QSPI clock. */ > cqspi->num_clks = devm_clk_bulk_get_all(dev, &cqspi->clks); > if (cqspi->num_clks < 0) { > dev_err(dev, "Cannot claim QSPI clock: %u\n", cqspi->num_clks); > return -EINVAL; > } > This way, the code will look simpler and clearer. How do you think > about it. I'm not clear how enable and disable would then work?
On 2023/5/31 21:20, Mark Brown wrote: > On Wed, May 31, 2023 at 02:19:16PM +0800, William Qiu wrote: >> On 2023/5/30 18:33, Mark Brown wrote: > >> > You could always specify a different array of clocks depending on which >> > compatible the driver sees, just like you'd conditionally request clocks >> > individually. > >> If specify a different array of clocks depending on which compatible >> the driver sees, since there will also be clock operations in the suspend >> and resume interfaces, this can make the code look complicated. > > If you store the clock count and array in the driver data that should be > fairly simple I think. > >> as following: > >> /* Obtain QSPI clock. */ >> cqspi->num_clks = devm_clk_bulk_get_all(dev, &cqspi->clks); >> if (cqspi->num_clks < 0) { >> dev_err(dev, "Cannot claim QSPI clock: %u\n", cqspi->num_clks); >> return -EINVAL; >> } > >> This way, the code will look simpler and clearer. How do you think >> about it. > > I'm not clear how enable and disable would then work? enable use this API: clk_bulk_prepare_enable(dev->num_clks, dev->clks); then disable: clk_bulk_disable_unprepare(dev->num_clks, dev->clks); But I'll first try specify a different array of clocks depending on which compatible the driver sees first. Best regards, William
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 6ddb2dfc0f00..c6430fb3a0a4 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1624,6 +1624,7 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi) static int cqspi_probe(struct platform_device *pdev) { const struct cqspi_driver_platdata *ddata; + struct clk *qspi_ahb, *qspi_apb; struct reset_control *rstc, *rstc_ocp, *rstc_ref; struct device *dev = &pdev->dev; struct spi_master *master; @@ -1715,6 +1716,32 @@ static int cqspi_probe(struct platform_device *pdev) } if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { + qspi_ahb = devm_clk_get(dev, "qspi-ahb"); + if (IS_ERR(qspi_ahb)) { + dev_err(dev, "Cannot claim QSPI_AHB clock.\n"); + ret = PTR_ERR(qspi_ahb); + return ret; + } + + ret = clk_prepare_enable(qspi_ahb); + if (ret) { + dev_err(dev, "Cannot enable QSPI AHB clock.\n"); + goto probe_clk_failed; + } + + qspi_apb = devm_clk_get(dev, "qspi-apb"); + if (IS_ERR(qspi_apb)) { + dev_err(dev, "Cannot claim QSPI_APB clock.\n"); + ret = PTR_ERR(qspi_apb); + return ret; + } + + ret = clk_prepare_enable(qspi_apb); + if (ret) { + dev_err(dev, "Cannot enable QSPI APB clock.\n"); + goto probe_clk_failed; + } + rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref"); if (IS_ERR(rstc_ref)) { ret = PTR_ERR(rstc_ref);