Message ID | 20230519155602.6642-2-quic_jkona@quicinc.com |
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State | New |
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Fri, 19 May 2023 15:57:04 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34JFv4BU020291 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 19 May 2023 15:57:04 GMT Received: from hu-jkona-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 19 May 2023 08:56:59 -0700 From: Jagadeesh Kona <quic_jkona@quicinc.com> To: Andy Gross <agross@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org> CC: Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, <linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, Taniya Das <quic_tdas@quicinc.com>, "Jagadeesh Kona" <quic_jkona@quicinc.com>, Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Subject: [PATCH 1/4] clk: qcom: clk-alpha-pll: Add support for rivian ole pll ops Date: Fri, 19 May 2023 21:25:59 +0530 Message-ID: <20230519155602.6642-2-quic_jkona@quicinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230519155602.6642-1-quic_jkona@quicinc.com> References: <20230519155602.6642-1-quic_jkona@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: KBCBptDrnOwd_n1tYceXTMIGM7fU_lKS X-Proofpoint-ORIG-GUID: KBCBptDrnOwd_n1tYceXTMIGM7fU_lKS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-19_11,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 phishscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 mlxscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 impostorscore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305190135 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766339367174106159?= X-GMAIL-MSGID: =?utf-8?q?1766339367174106159?= |
Series |
Add camera clock controller support for SM8550
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Commit Message
Jagadeesh Kona
May 19, 2023, 3:55 p.m. UTC
Add support for rivian ole pll ops and ole pll registers to configure and control the rivian ole pll. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> --- drivers/clk/qcom/clk-alpha-pll.h | 4 ++++ 1 file changed, 4 insertions(+)
Comments
On 19.05.2023 17:55, Jagadeesh Kona wrote: > Add support for rivian ole pll ops and ole pll registers to > configure and control the rivian ole pll. > > Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > --- > drivers/clk/qcom/clk-alpha-pll.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h > index 4d9b6d5b7062..e6df398bee6d 100644 > --- a/drivers/clk/qcom/clk-alpha-pll.h > +++ b/drivers/clk/qcom/clk-alpha-pll.h > @@ -24,6 +24,7 @@ enum { > CLK_ALPHA_PLL_TYPE_LUCID_EVO, > CLK_ALPHA_PLL_TYPE_LUCID_OLE, > CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, > + CLK_ALPHA_PLL_TYPE_RIVIAN_OLE = CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, This makes sense The rest is just sugar syntax, I don't think it makes sense to keep adding meaningless defines.. Konrad > CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, > CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, > CLK_ALPHA_PLL_TYPE_STROMER, > @@ -181,6 +182,7 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; > #define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops > > extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; > +#define clk_alpha_pll_rivian_ole_ops clk_alpha_pll_rivian_evo_ops > #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops > > void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, > @@ -202,6 +204,8 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma > clk_lucid_evo_pll_configure(pll, regmap, config) > void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, > const struct alpha_pll_config *config); > +#define clk_rivian_ole_pll_configure(pll, regmap, config) \ > + clk_rivian_evo_pll_configure(pll, regmap, config) > void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, > const struct alpha_pll_config *config); >
Hi Konrad, Thanks for your review! On 5/19/2023 10:19 PM, Konrad Dybcio wrote: > > > On 19.05.2023 17:55, Jagadeesh Kona wrote: >> Add support for rivian ole pll ops and ole pll registers to >> configure and control the rivian ole pll. >> >> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >> --- >> drivers/clk/qcom/clk-alpha-pll.h | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h >> index 4d9b6d5b7062..e6df398bee6d 100644 >> --- a/drivers/clk/qcom/clk-alpha-pll.h >> +++ b/drivers/clk/qcom/clk-alpha-pll.h >> @@ -24,6 +24,7 @@ enum { >> CLK_ALPHA_PLL_TYPE_LUCID_EVO, >> CLK_ALPHA_PLL_TYPE_LUCID_OLE, >> CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, >> + CLK_ALPHA_PLL_TYPE_RIVIAN_OLE = CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, > This makes sense > > The rest is just sugar syntax, I don't think it makes sense to keep > adding meaningless defines.. > Yes, will remove these and reuse existing ops in next series. > Konrad >> CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, >> CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, >> CLK_ALPHA_PLL_TYPE_STROMER, >> @@ -181,6 +182,7 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; >> #define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops >> >> extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; >> +#define clk_alpha_pll_rivian_ole_ops clk_alpha_pll_rivian_evo_ops >> #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops >> >> void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, >> @@ -202,6 +204,8 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma >> clk_lucid_evo_pll_configure(pll, regmap, config) >> void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, >> const struct alpha_pll_config *config); >> +#define clk_rivian_ole_pll_configure(pll, regmap, config) \ >> + clk_rivian_evo_pll_configure(pll, regmap, config) >> void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, >> const struct alpha_pll_config *config); >> Thanks & Regards, Jagadeesh
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 4d9b6d5b7062..e6df398bee6d 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -24,6 +24,7 @@ enum { CLK_ALPHA_PLL_TYPE_LUCID_EVO, CLK_ALPHA_PLL_TYPE_LUCID_OLE, CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, + CLK_ALPHA_PLL_TYPE_RIVIAN_OLE = CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, CLK_ALPHA_PLL_TYPE_STROMER, @@ -181,6 +182,7 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; #define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; +#define clk_alpha_pll_rivian_ole_ops clk_alpha_pll_rivian_evo_ops #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, @@ -202,6 +204,8 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma clk_lucid_evo_pll_configure(pll, regmap, config) void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); +#define clk_rivian_ole_pll_configure(pll, regmap, config) \ + clk_rivian_evo_pll_configure(pll, regmap, config) void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config);