[net-next,v2,4/7] net: dsa: mv88e6xxx: add field to specify internal phys layout
Commit Message
From: Alexis Lothoré <alexis.lothore@bootlin.com>
mv88e6xxx currently assumes that switch equipped with internal phys have
those phys mapped contiguously starting from port 0 (see
mv88e6xxx_phy_is_internal). However, some switches have internal PHYs but
NOT starting from port 0. For example 88e6393X, 88E6193X and 88E6191X have
integrated PHYs available on ports 1 to 8
To properly support this offset, add a new field to allow specifying an
internal PHYs layout. If field is not set, default layout is assumed (start
at port 0)
Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
---
drivers/net/dsa/mv88e6xxx/chip.c | 4 +++-
drivers/net/dsa/mv88e6xxx/chip.h | 5 +++++
drivers/net/dsa/mv88e6xxx/global2.c | 6 +++++-
3 files changed, 13 insertions(+), 2 deletions(-)
Comments
> @@ -1198,13 +1198,17 @@ int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
> {
> int phy, irq;
>
> - for (phy = 0; phy < chip->info->num_internal_phys; phy++) {
> + for (phy = chip->info->internal_phys_offset;
> + phy <
> + chip->info->num_internal_phys + chip->info->internal_phys_offset;
> + phy++) {
The code style is not so nice. How about moving this addition out of
the for loop, it is static anyway. And then you can avoid splitting
the expression over multiple lines.
> irq = irq_find_mapping(chip->g2_irq.domain, phy);
> if (irq < 0)
> return irq;
>
> bus->irq[chip->info->phy_base_addr + phy] = irq;
> }
> +
No whitespace changed please.
Andrew
---
pw-bot: cr
@@ -465,7 +465,9 @@ static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
{
- return port < chip->info->num_internal_phys;
+ return port >= chip->info->internal_phys_offset &&
+ port < chip->info->num_internal_phys +
+ chip->info->internal_phys_offset;
}
static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
@@ -167,6 +167,11 @@ struct mv88e6xxx_info {
/* Supports PTP */
bool ptp_support;
+
+ /* Internal PHY start index. 0 means that internal PHYs range starts at
+ * port 0, 1 means internal PHYs range starts at port 1, etc
+ */
+ unsigned int internal_phys_offset;
};
struct mv88e6xxx_atu_entry {
@@ -1198,13 +1198,17 @@ int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
{
int phy, irq;
- for (phy = 0; phy < chip->info->num_internal_phys; phy++) {
+ for (phy = chip->info->internal_phys_offset;
+ phy <
+ chip->info->num_internal_phys + chip->info->internal_phys_offset;
+ phy++) {
irq = irq_find_mapping(chip->g2_irq.domain, phy);
if (irq < 0)
return irq;
bus->irq[chip->info->phy_base_addr + phy] = irq;
}
+
return 0;
}