diff mbox series

[4/6] drm/msm/a6xx: Improve GMU force shutdown sequence

Message ID 20230517-topic-a7xx_prep-v1-4-7a964f2e99c2@linaro.org
State New
Headers
Series Adreno QoL changes |

Commit Message

Konrad Dybcio May 17, 2023, 4:50 p.m. UTC 
  The GMU force shutdown sequence involves some additional register cleanup
which was not implemented previously. Do so.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 7 +++++++
 1 file changed, 7 insertions(+)

Comments

kernel test robot May 17, 2023, 10:19 p.m. UTC | #1 
Hi Konrad,

kernel test robot noticed the following build errors:

[auto build test ERROR on 065efa589871e93b6610c70c1e9de274ef1f1ba2]

url:    https://github.com/intel-lab-lkp/linux/commits/Konrad-Dybcio/drm-msm-a6xx-Explain-CP_PROTECT_CNTL-writes-in-a6xx_set_cp_protect/20230518-010130
base:   065efa589871e93b6610c70c1e9de274ef1f1ba2
patch link:    https://lore.kernel.org/r/20230517-topic-a7xx_prep-v1-4-7a964f2e99c2%40linaro.org
patch subject: [PATCH 4/6] drm/msm/a6xx: Improve GMU force shutdown sequence
config: mips-allyesconfig
compiler: mips-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/c8d08c2d02fc0a1ef0cdcc93d041e3802e01904e
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Konrad-Dybcio/drm-msm-a6xx-Explain-CP_PROTECT_CNTL-writes-in-a6xx_set_cp_protect/20230518-010130
        git checkout c8d08c2d02fc0a1ef0cdcc93d041e3802e01904e
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=mips olddefconfig
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=mips SHELL=/bin/bash drivers/gpu/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202305180505.bG7RPhZo-lkp@intel.com/

All errors (new ones prefixed by >>):

   drivers/gpu/drm/msm/adreno/a6xx_gmu.c: In function 'a6xx_gmu_force_off':
>> drivers/gpu/drm/msm/adreno/a6xx_gmu.c:934:24: error: 'REG_A6XX_GMU_AHB_FENCE_STATUS_CLR' undeclared (first use in this function); did you mean 'REG_A6XX_GMU_AHB_FENCE_STATUS'?
     934 |         gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS_CLR, 0x7);
         |                        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
         |                        REG_A6XX_GMU_AHB_FENCE_STATUS
   drivers/gpu/drm/msm/adreno/a6xx_gmu.c:934:24: note: each undeclared identifier is reported only once for each function it appears in


vim +934 drivers/gpu/drm/msm/adreno/a6xx_gmu.c

   913	
   914	/* Force the GMU off in case it isn't responsive */
   915	static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
   916	{
   917		struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
   918		struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
   919		struct msm_gpu *gpu = &adreno_gpu->base;
   920	
   921		/* Flush all the queues */
   922		a6xx_hfi_stop(gmu);
   923	
   924		/* Stop the interrupts */
   925		a6xx_gmu_irq_disable(gmu);
   926	
   927		/* Force off SPTP in case the GMU is managing it */
   928		a6xx_sptprac_disable(gmu);
   929	
   930		/* Make sure there are no outstanding RPMh votes */
   931		a6xx_gmu_rpmh_off(gmu);
   932	
   933		/* Clear the WRITEDROPPED fields and put fence into allow mode */
 > 934		gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS_CLR, 0x7);
   935		gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
   936	
   937		/* Make sure the above writes go through */
   938		wmb();
   939	
   940		/* Halt the gmu cm3 core */
   941		gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
   942	
   943		a6xx_bus_clear_pending_transactions(adreno_gpu, true);
   944	
   945		/* Reset GPU core blocks */
   946		gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, 1);
   947		udelay(100);
   948	}
   949
diff mbox series

Patch

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index ea6d671e7c6c..8004b582e45f 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -930,6 +930,13 @@  static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
 	/* Make sure there are no outstanding RPMh votes */
 	a6xx_gmu_rpmh_off(gmu);
 
+	/* Clear the WRITEDROPPED fields and put fence into allow mode */
+	gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS_CLR, 0x7);
+	gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
+
+	/* Make sure the above writes go through */
+	wmb();
+
 	/* Halt the gmu cm3 core */
 	gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);