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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: [PATCH 1/2] arm64: dts: qcom: sm8550-qrd: add PCIe0
Date: Tue, 16 May 2023 15:30:10 +0200
Message-Id: <20230516133011.108093-1-krzysztof.kozlowski@linaro.org>
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[1/2] arm64: dts: qcom: sm8550-qrd: add PCIe0
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Commit Message
Krzysztof Kozlowski
May 16, 2023, 1:30 p.m. UTC
Add PCIe0 nodes used with WCN7851 device. The PCIe1 is not connected,
thus skip pcie_1_phy_aux_clk input clock to GCC.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 32 +++++++++++++++++++++++++
1 file changed, 32 insertions(+)
Comments
On 16/05/2023 15:30, Krzysztof Kozlowski wrote: > Add PCIe0 nodes used with WCN7851 device. The PCIe1 is not connected, > thus skip pcie_1_phy_aux_clk input clock to GCC. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 32 +++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
On 16/05/2023 15:30, Krzysztof Kozlowski wrote: > Add missing parts of USB stack to enable USB OTG mode. The QRD8550 > comes with one USB Type-C port. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 52 ++++++++++++++++++++++++- > 1 file changed, 51 insertions(+), 1 deletion(-) Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
On Tue, 16 May 2023 at 16:30, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > Add PCIe0 nodes used with WCN7851 device. The PCIe1 is not connected, > thus skip pcie_1_phy_aux_clk input clock to GCC. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 32 +++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts > index ccc58e6b45bd..e7a2bc5d788b 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts > +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts > @@ -385,6 +385,38 @@ vreg_l3g_1p2: ldo3 { > }; > }; > > +&gcc { > + clocks = <&bi_tcxo_div2>, <&sleep_clk>, > + <&pcie0_phy>, > + <&pcie1_phy>, > + <0>, > + <&ufs_mem_phy 0>, > + <&ufs_mem_phy 1>, > + <&ufs_mem_phy 2>, > + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; > +}; Is there any reason to disable the PCIe1 PHY AUX clock here? I mean, the PCIe1 is still enabled in the hardware. > + > +&pcie_1_phy_aux_clk { > + status = "disabled"; > +}; > + > +&pcie0 { > + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; > + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; > + > + pinctrl-0 = <&pcie0_default_state>; > + pinctrl-names = "default"; > + > + status = "okay"; > +}; > + > +&pcie0_phy { > + vdda-phy-supply = <&vreg_l1e_0p88>; > + vdda-pll-supply = <&vreg_l3e_1p2>; > + > + status = "okay"; > +}; > + > &qupv3_id_0 { > status = "okay"; > }; > -- > 2.34.1 >
On 16/05/2023 18:39, Dmitry Baryshkov wrote: > On Tue, 16 May 2023 at 16:30, Krzysztof Kozlowski > <krzysztof.kozlowski@linaro.org> wrote: >> >> Add PCIe0 nodes used with WCN7851 device. The PCIe1 is not connected, >> thus skip pcie_1_phy_aux_clk input clock to GCC. >> >> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> --- >> arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 32 +++++++++++++++++++++++++ >> 1 file changed, 32 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts >> index ccc58e6b45bd..e7a2bc5d788b 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts >> +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts >> @@ -385,6 +385,38 @@ vreg_l3g_1p2: ldo3 { >> }; >> }; >> >> +&gcc { >> + clocks = <&bi_tcxo_div2>, <&sleep_clk>, >> + <&pcie0_phy>, >> + <&pcie1_phy>, >> + <0>, >> + <&ufs_mem_phy 0>, >> + <&ufs_mem_phy 1>, >> + <&ufs_mem_phy 2>, >> + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; >> +}; > > Is there any reason to disable the PCIe1 PHY AUX clock here? I mean, > the PCIe1 is still enabled in the hardware. I was thinking about this. The AUX clock seems to be an external clock, although I could not find it in schematics. I assume that on QRD8550 it could be missing, if it is really external. OTOH, downstream DTS did not seem to care... Best regards, Krzysztof
On Tue, 16 May 2023 at 19:43, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 16/05/2023 18:39, Dmitry Baryshkov wrote: > > On Tue, 16 May 2023 at 16:30, Krzysztof Kozlowski > > <krzysztof.kozlowski@linaro.org> wrote: > >> > >> Add PCIe0 nodes used with WCN7851 device. The PCIe1 is not connected, > >> thus skip pcie_1_phy_aux_clk input clock to GCC. > >> > >> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > >> --- > >> arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 32 +++++++++++++++++++++++++ > >> 1 file changed, 32 insertions(+) > >> > >> diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts > >> index ccc58e6b45bd..e7a2bc5d788b 100644 > >> --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts > >> +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts > >> @@ -385,6 +385,38 @@ vreg_l3g_1p2: ldo3 { > >> }; > >> }; > >> > >> +&gcc { > >> + clocks = <&bi_tcxo_div2>, <&sleep_clk>, > >> + <&pcie0_phy>, > >> + <&pcie1_phy>, > >> + <0>, > >> + <&ufs_mem_phy 0>, > >> + <&ufs_mem_phy 1>, > >> + <&ufs_mem_phy 2>, > >> + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; > >> +}; > > > > Is there any reason to disable the PCIe1 PHY AUX clock here? I mean, > > the PCIe1 is still enabled in the hardware. > > I was thinking about this. The AUX clock seems to be an external clock, > although I could not find it in schematics. I assume that on QRD8550 it > could be missing, if it is really external. OTOH, downstream DTS did not > seem to care... I might be completely wrong here, but I think that AUX clock is yet another clock provided by the PHY to the GCC, which we were just ignoring for now. For example, for sm8450 we have <0> there. I don't see it as an external clock, so I think it is internal to the SoC.
On 16/05/2023 19:15, Dmitry Baryshkov wrote: > On Tue, 16 May 2023 at 19:43, Krzysztof Kozlowski > <krzysztof.kozlowski@linaro.org> wrote: >> >> On 16/05/2023 18:39, Dmitry Baryshkov wrote: >>> On Tue, 16 May 2023 at 16:30, Krzysztof Kozlowski >>> <krzysztof.kozlowski@linaro.org> wrote: >>>> >>>> Add PCIe0 nodes used with WCN7851 device. The PCIe1 is not connected, >>>> thus skip pcie_1_phy_aux_clk input clock to GCC. >>>> >>>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >>>> --- >>>> arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 32 +++++++++++++++++++++++++ >>>> 1 file changed, 32 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts >>>> index ccc58e6b45bd..e7a2bc5d788b 100644 >>>> --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts >>>> +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts >>>> @@ -385,6 +385,38 @@ vreg_l3g_1p2: ldo3 { >>>> }; >>>> }; >>>> >>>> +&gcc { >>>> + clocks = <&bi_tcxo_div2>, <&sleep_clk>, >>>> + <&pcie0_phy>, >>>> + <&pcie1_phy>, >>>> + <0>, >>>> + <&ufs_mem_phy 0>, >>>> + <&ufs_mem_phy 1>, >>>> + <&ufs_mem_phy 2>, >>>> + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; >>>> +}; >>> >>> Is there any reason to disable the PCIe1 PHY AUX clock here? I mean, >>> the PCIe1 is still enabled in the hardware. >> >> I was thinking about this. The AUX clock seems to be an external clock, >> although I could not find it in schematics. I assume that on QRD8550 it >> could be missing, if it is really external. OTOH, downstream DTS did not >> seem to care... > > I might be completely wrong here, but I think that AUX clock is yet > another clock provided by the PHY to the GCC, which we were just > ignoring for now. For example, for sm8450 we have <0> there. I don't > see it as an external clock, so I think it is internal to the SoC. Hm, in that case it would make sense to keep it here. It's frequency, with some safe choice, could also go to DTSI. Best regards, Krzysztof
On Tue, 16 May 2023 15:30:10 +0200, Krzysztof Kozlowski wrote: > Add PCIe0 nodes used with WCN7851 device. The PCIe1 is not connected, > thus skip pcie_1_phy_aux_clk input clock to GCC. > > Applied, thanks! [1/2] arm64: dts: qcom: sm8550-qrd: add PCIe0 commit: b8ae83eb0c9648a3f9c386cfb191e31139050143 [2/2] arm64: dts: qcom: sm8550-qrd: add USB OTG commit: d97a6332c5841df4fb03aef996a7139465d68ca8 Best regards,
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index ccc58e6b45bd..e7a2bc5d788b 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -385,6 +385,38 @@ vreg_l3g_1p2: ldo3 { }; }; +&gcc { + clocks = <&bi_tcxo_div2>, <&sleep_clk>, + <&pcie0_phy>, + <&pcie1_phy>, + <0>, + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; +}; + +&pcie_1_phy_aux_clk { + status = "disabled"; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; };