arm64: dts: marvell: add missing cache properties
Commit Message
As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:
ac5-98dx35xx-rd.dtb: l2-cache: 'cache-unified' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Please take the patch via sub-arch SoC tree.
---
arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 1 +
arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 1 +
arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 2 ++
arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 2 ++
4 files changed, 6 insertions(+)
Comments
On 22/04/2023 00:31, Krzysztof Kozlowski wrote:
> As all level 2 and level 3 caches are unified, add required
> cache-unified properties to fix warnings like:
>
> ac5-98dx35xx-rd.dtb: l2-cache: 'cache-unified' is a required property
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> ---
>
> Please take the patch via sub-arch SoC tree.
Hi Andrew and Gregory,
Could you grab this one?
Best regards,
Krzysztof
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> writes:
> On 22/04/2023 00:31, Krzysztof Kozlowski wrote:
>> As all level 2 and level 3 caches are unified, add required
>> cache-unified properties to fix warnings like:
>>
>> ac5-98dx35xx-rd.dtb: l2-cache: 'cache-unified' is a required property
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>
>> ---
>>
>> Please take the patch via sub-arch SoC tree.
>
> Hi Andrew and Gregory,
>
> Could you grab this one?
Applied on mvebu/dt64
Thanks,
Gregory
>
> Best regards,
> Krzysztof
>
@@ -50,6 +50,7 @@ cpu1: cpu@1 {
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
};
};
@@ -52,6 +52,7 @@ l2: l2-cache {
cache-line-size = <64>;
cache-sets = <512>;
cache-level = <2>;
+ cache-unified;
};
};
@@ -82,6 +82,7 @@ l2_0: l2-cache0 {
cache-line-size = <64>;
cache-sets = <512>;
cache-level = <2>;
+ cache-unified;
};
l2_1: l2-cache1 {
@@ -90,6 +91,7 @@ l2_1: l2-cache1 {
cache-line-size = <64>;
cache-sets = <512>;
cache-level = <2>;
+ cache-unified;
};
};
};
@@ -82,6 +82,7 @@ l2_0: l2-cache0 {
cache-line-size = <64>;
cache-sets = <512>;
cache-level = <2>;
+ cache-unified;
};
l2_1: l2-cache1 {
@@ -90,6 +91,7 @@ l2_1: l2-cache1 {
cache-line-size = <64>;
cache-sets = <512>;
cache-level = <2>;
+ cache-unified;
};
};
};