arm64: zynqmp: Switch to amd.com emails
Commit Message
Update my and DPs email address to match current setup.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts | 5 +++--
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 2 +-
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 2 +-
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 2 +-
arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 5 +++--
arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts | 5 +++--
arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 5 +++--
arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 7 ++++---
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 2 +-
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 2 +-
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 5 +++--
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 5 +++--
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 7 ++++---
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 +-
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 5 +++--
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts | 5 +++--
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 +-
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 2 +-
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 2 +-
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 2 +-
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 2 +-
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 2 +-
arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts | 7 ++++---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 5 +++--
24 files changed, 51 insertions(+), 39 deletions(-)
Comments
On 16/05/2023 15:41, Michal Simek wrote:
> Update my and DPs email address to match current setup.
>
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
>
> arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 7 ++++---
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 7 ++++---
> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts | 7 ++++---
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 5 +++--
> 24 files changed, 51 insertions(+), 39 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts b/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
> index 88aa06fa78a8..1495272e5668 100644
> --- a/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
> +++ b/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
> @@ -2,9 +2,10 @@
> /*
> * dts file for Avnet Ultra96 rev1
> *
> - * (C) Copyright 2018, Xilinx, Inc.
> + * (C) Copyright 2018 - 2022, Xilinx, Inc.
> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
I think these should be split. Your commit suggests only update to email
but you add copyrights. While email change is trivial, the copyright
change is not (at least not for everyone and for every legal system).
What's more, there were no changes to this file after 2018. What
copyrighted work did you add in 2019, 2020, 2021, 2022 and 2023? For
this file clear: NAK
Same concerns for most of other files.
Best regards,
Krzysztof
On 5/16/23 18:05, Krzysztof Kozlowski wrote:
> On 16/05/2023 15:41, Michal Simek wrote:
>> Update my and DPs email address to match current setup.
>>
>> Signed-off-by: Michal Simek <michal.simek@amd.com>
>> ---
>>
>> arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts | 5 +++--
>> arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 2 +-
>> arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 2 +-
>> arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 2 +-
>> arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 5 +++--
>> arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts | 5 +++--
>> arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 5 +++--
>> arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 7 ++++---
>> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 2 +-
>> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 2 +-
>> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 5 +++--
>> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 5 +++--
>> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 7 ++++---
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 +-
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 5 +++--
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts | 5 +++--
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 +-
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 2 +-
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 2 +-
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 2 +-
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 2 +-
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 2 +-
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts | 7 ++++---
>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 5 +++--
>> 24 files changed, 51 insertions(+), 39 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts b/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
>> index 88aa06fa78a8..1495272e5668 100644
>> --- a/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
>> +++ b/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
>> @@ -2,9 +2,10 @@
>> /*
>> * dts file for Avnet Ultra96 rev1
>> *
>> - * (C) Copyright 2018, Xilinx, Inc.
>> + * (C) Copyright 2018 - 2022, Xilinx, Inc.
>> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
>
> I think these should be split. Your commit suggests only update to email
> but you add copyrights. While email change is trivial,
ok
> the copyright
> change is not (at least not for everyone and for every legal system).
>
> What's more, there were no changes to this file after 2018. What
> copyrighted work did you add in 2019, 2020, 2021, 2022 and 2023? For
> this file clear: NAK
All these files are regularly updated in soc vendor tree. I can do stats to
double check every file but I am quite sure that every year we did touch these
files at least with single line of change (and not just copyright update).
It means at least it is not big concern from me that we created file in 2018 and
then touch them this year.
The question is if this is valid argument which could be accepted upstream.
TBH I don't mind too much because primary reason for this patch was updating my
email address.
>
> Same concerns for most of other files.
Sure
Thanks,
Michal
On 16/05/2023 19:20, Michal Simek wrote:
>
>
> On 5/16/23 18:05, Krzysztof Kozlowski wrote:
>> On 16/05/2023 15:41, Michal Simek wrote:
>>> Update my and DPs email address to match current setup.
>>>
>>> Signed-off-by: Michal Simek <michal.simek@amd.com>
>>> ---
>>>
>>> arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts | 5 +++--
>>> arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 2 +-
>>> arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 2 +-
>>> arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 2 +-
>>> arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 5 +++--
>>> arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts | 5 +++--
>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 5 +++--
>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 7 ++++---
>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 2 +-
>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 2 +-
>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 5 +++--
>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 5 +++--
>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 7 ++++---
>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 +-
>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 5 +++--
>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts | 5 +++--
>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 +-
>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 2 +-
>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 2 +-
>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 2 +-
>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 2 +-
>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 2 +-
>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts | 7 ++++---
>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 5 +++--
>>> 24 files changed, 51 insertions(+), 39 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts b/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
>>> index 88aa06fa78a8..1495272e5668 100644
>>> --- a/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
>>> +++ b/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
>>> @@ -2,9 +2,10 @@
>>> /*
>>> * dts file for Avnet Ultra96 rev1
>>> *
>>> - * (C) Copyright 2018, Xilinx, Inc.
>>> + * (C) Copyright 2018 - 2022, Xilinx, Inc.
>>> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
>>
>> I think these should be split. Your commit suggests only update to email
>> but you add copyrights. While email change is trivial,
>
> ok
>
>> the copyright
>> change is not (at least not for everyone and for every legal system).
>>
>> What's more, there were no changes to this file after 2018. What
>> copyrighted work did you add in 2019, 2020, 2021, 2022 and 2023? For
>> this file clear: NAK
>
> All these files are regularly updated in soc vendor tree. I can do stats to
> double check every file but I am quite sure that every year we did touch these
> files at least with single line of change (and not just copyright update).
I checked. Copyrights, if you need them, should be added in a meaningful
way, so with copyrightable work. This file has 0.
For other files, if you want to add copyrights for every trivial change,
this will lead to adding other people's copyrights as well...
> It means at least it is not big concern from me that we created file in 2018 and
> then touch them this year.
> The question is if this is valid argument which could be accepted upstream.
> TBH I don't mind too much because primary reason for this patch was updating my
> email address.
>
Best regards,
Krzysztof
> -----Original Message-----
> From: Simek, Michal <michal.simek@amd.com>
> Sent: Tuesday, May 16, 2023 7:12 PM
> To: linux-kernel@vger.kernel.org; monstr@monstr.eu; michal.simek@xilinx.com;
> git@xilinx.com
> Cc: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>; Andrew Davis
> <afd@ti.com>; Conor Dooley <conor+dt@kernel.org>; Geert Uytterhoeven
> <geert+renesas@glider.be>; Katakam, Harini <harini.katakam@amd.com>;
> Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Laurent Pinchart
> <laurent.pinchart@ideasonboard.com>; Michael Grzeschik
> <m.grzeschik@pengutronix.de>; Michael Tretter <m.tretter@pengutronix.de>;
> Gajjar, Parth <parth.gajjar@amd.com>; Piyush Mehta
> <piyush.mehta@xilinx.com>; Rob Herring <robh+dt@kernel.org>; Robert
> Hancock <robert.hancock@calian.com>; Srinivas Neeli
> <srinivas.neeli@xilinx.com>; Shah, Tanmay <tanmay.shah@amd.com>; Sagar,
> Vishal <vishal.sagar@amd.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Subject: [PATCH] arm64: zynqmp: Switch to amd.com emails
>
> Update my and DPs email address to match current setup.
>
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
>
> arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 7 ++++---
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 7 ++++---
> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts | 7 ++++---
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 5 +++--
> 24 files changed, 51 insertions(+), 39 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
> b/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
> index 88aa06fa78a8..1495272e5668 100644
> --- a/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
> +++ b/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
> @@ -2,9 +2,10 @@
> /*
> * dts file for Avnet Ultra96 rev1
> *
> - * (C) Copyright 2018, Xilinx, Inc.
> + * (C) Copyright 2018 - 2022, Xilinx, Inc.
> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> */
>
> /dts-v1/;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> index 719ea5d5ae88..f04716841a0c 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> @@ -5,7 +5,7 @@
> * (C) Copyright 2017 - 2022, Xilinx, Inc.
> * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> */
>
> #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> index bebbe955eec1..669fe6084f3f 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> @@ -9,7 +9,7 @@
> * "Y" - A01 board modified with legacy interposer (Nexperia)
> * "Z" - A01 board modified with Diode interposer
> *
> - * Michal Simek <michal.simek@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> */
>
> #include <dt-bindings/gpio/gpio.h>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> index 8e66448f35a9..7886a19139ee 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> @@ -4,7 +4,7 @@
> *
> * (C) Copyright 2020 - 2021, Xilinx, Inc.
> *
> - * Michal Simek <michal.simek@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> */
>
> #include <dt-bindings/gpio/gpio.h>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
> b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
> index 464e28bf078a..8d1c54e00556 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
> @@ -2,9 +2,10 @@
> /*
> * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
> *
> - * (C) Copyright 2020 - 2021, Xilinx, Inc.
> + * (C) Copyright 2020 - 2022, Xilinx, Inc.
> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> */
>
> /dts-v1/;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts
> b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts
> index c70966c1f344..664ea7d99049 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts
> @@ -2,9 +2,10 @@
> /*
> * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A
> *
> - * (C) Copyright 2020 - 2021, Xilinx, Inc.
> + * (C) Copyright 2020 - 2022, Xilinx, Inc.
> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> */
>
> #include "zynqmp-sm-k26-revA.dts"
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
> b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
> index f1598527e5ec..774fb773886e 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
> @@ -2,9 +2,10 @@
> /*
> * dts file for Xilinx ZynqMP ZC1232
> *
> - * (C) Copyright 2017 - 2021, Xilinx, Inc.
> + * (C) Copyright 2017 - 2022, Xilinx, Inc.
> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> */
>
> /dts-v1/;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
> b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
> index 04efa1683eaa..7c27b0e9a522 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
> @@ -2,10 +2,11 @@
> /*
> * dts file for Xilinx ZynqMP ZC1254
> *
> - * (C) Copyright 2015 - 2021, Xilinx, Inc.
> + * (C) Copyright 2015 - 2022, Xilinx, Inc.
> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xilinx.com>
> - * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> + * Siva Durga Prasad Paladug <siva.durga.prasad.paladugu@amd.com>
There is a typo in my name here and everywhere in the patch, Please fix this. Paladug -> Paladugu
Thanks,
DP
@@ -2,9 +2,10 @@
/*
* dts file for Avnet Ultra96 rev1
*
- * (C) Copyright 2018, Xilinx, Inc.
+ * (C) Copyright 2018 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@@ -5,7 +5,7 @@
* (C) Copyright 2017 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*/
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
@@ -9,7 +9,7 @@
* "Y" - A01 board modified with legacy interposer (Nexperia)
* "Z" - A01 board modified with Diode interposer
*
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*/
#include <dt-bindings/gpio/gpio.h>
@@ -4,7 +4,7 @@
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*/
#include <dt-bindings/gpio/gpio.h>
@@ -2,9 +2,10 @@
/*
* dts file for Xilinx ZynqMP SM-K26 rev1/B/A
*
- * (C) Copyright 2020 - 2021, Xilinx, Inc.
+ * (C) Copyright 2020 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@@ -2,9 +2,10 @@
/*
* dts file for Xilinx ZynqMP SMK-K26 rev1/B/A
*
- * (C) Copyright 2020 - 2021, Xilinx, Inc.
+ * (C) Copyright 2020 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*/
#include "zynqmp-sm-k26-revA.dts"
@@ -2,9 +2,10 @@
/*
* dts file for Xilinx ZynqMP ZC1232
*
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@@ -2,10 +2,11 @@
/*
* dts file for Xilinx ZynqMP ZC1254
*
- * (C) Copyright 2015 - 2021, Xilinx, Inc.
+ * (C) Copyright 2015 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad Paladug <siva.durga.prasad.paladugu@amd.com>
*/
/dts-v1/;
@@ -4,7 +4,7 @@
*
* (C) Copyright 2015 - 2021, Xilinx, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@@ -4,7 +4,7 @@
*
* (C) Copyright 2015 - 2021, Xilinx, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@@ -2,9 +2,10 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm017-dc3
*
- * (C) Copyright 2016 - 2021, Xilinx, Inc.
+ * (C) Copyright 2016 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@@ -2,9 +2,10 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm018-dc4
*
- * (C) Copyright 2015 - 2021, Xilinx, Inc.
+ * (C) Copyright 2015 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@@ -2,10 +2,11 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm019-dc5
*
- * (C) Copyright 2015 - 2021, Xilinx, Inc.
+ * (C) Copyright 2015 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
- * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladug <siva.durga.prasad.paladugu@amd.com>
+ * Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@@ -4,7 +4,7 @@
*
* (C) Copyright 2016 - 2021, Xilinx, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
* Nathalie Chan King Choy
*/
@@ -2,9 +2,10 @@
/*
* dts file for Xilinx ZynqMP ZCU102 Rev1.0
*
- * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ * (C) Copyright 2016 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*/
#include "zynqmp-zcu102-revB.dts"
@@ -2,9 +2,10 @@
/*
* dts file for Xilinx ZynqMP ZCU102 Rev1.1
*
- * (C) Copyright 2016 - 2020, Xilinx, Inc.
+ * (C) Copyright 2016 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*/
#include "zynqmp-zcu102-rev1.0.dts"
@@ -4,7 +4,7 @@
*
* (C) Copyright 2015 - 2021, Xilinx, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@@ -4,7 +4,7 @@
*
* (C) Copyright 2016 - 2021, Xilinx, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*/
#include "zynqmp-zcu102-revA.dts"
@@ -4,7 +4,7 @@
*
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@@ -4,7 +4,7 @@
*
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@@ -4,7 +4,7 @@
*
* (C) Copyright 2016 - 2021, Xilinx, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@@ -4,7 +4,7 @@
*
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
@@ -2,10 +2,11 @@
/*
* dts file for Xilinx ZynqMP ZC1275
*
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad Paladug <siva.durga.prasad.paladugu@amd.com>
*/
/dts-v1/;
@@ -2,9 +2,10 @@
/*
* dts file for Xilinx ZynqMP
*
- * (C) Copyright 2014 - 2021, Xilinx, Inc.
+ * (C) Copyright 2014 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as