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From: Achal Verma <a-verma1@ti.com>
To: Nishanth Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>,
Tero Kristo <kristo@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
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CC: <linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Achal Verma <a-verma1@ti.com>
Subject: [PATCH] arm64: dts: ti: k3-j7200: correct num-lanes requested for
PCIe
Date: Tue, 16 May 2023 11:52:12 +0530
Message-ID: <20230516062212.2635948-1-a-verma1@ti.com>
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arm64: dts: ti: k3-j7200: correct num-lanes requested for PCIe
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Commit Message
Achal Verma
May 16, 2023, 6:22 a.m. UTC
From: Matt Ranostay <mranostay@ti.com> J7200 has a limited 2x support for PCIe, and the properties should be updated as such. Signed-off-by: Matt Ranostay <mranostay@ti.com> Signed-off-by: Achal Verma <a-verma1@ti.com> --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Comments
Achal, On 16/05/23 11:52, Achal Verma wrote: > From: Matt Ranostay <mranostay@ti.com> > > J7200 has a limited 2x support for PCIe, and the properties should be > updated as such. According to J7200 Datasheet at [0], the SoC supports up to x4 PCIe lanes. Could you please clarify where the lanes are documented to be 2x? [0]: https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf > > Signed-off-by: Matt Ranostay <mranostay@ti.com> > Signed-off-by: Achal Verma <a-verma1@ti.com> > --- > arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi > index ef352e32f19d..5e62b431d6e8 100644 > --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi > @@ -729,7 +729,7 @@ pcie1_rc: pcie@2910000 { > device_type = "pci"; > ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; > max-link-speed = <3>; > - num-lanes = <4>; > + num-lanes = <2>; > power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; > clocks = <&k3_clks 240 6>; > clock-names = "fck"; > @@ -757,7 +757,7 @@ pcie1_ep: pcie-ep@2910000 { > interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; > ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; > max-link-speed = <3>; > - num-lanes = <4>; > + num-lanes = <2>; > power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; > clocks = <&k3_clks 240 6>; > clock-names = "fck";
On 5/16/2023 12:03 PM, Siddharth Vadapalli wrote: > Achal, > > On 16/05/23 11:52, Achal Verma wrote: >> From: Matt Ranostay <mranostay@ti.com> >> >> J7200 has a limited 2x support for PCIe, and the properties should be >> updated as such. > > According to J7200 Datasheet at [0], the SoC supports up to x4 PCIe lanes. Could > you please clarify where the lanes are documented to be 2x? > > [0]: https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf Yes, this patch should be dropped. No need to change lanes. Regards, Achal Verma > >> >> Signed-off-by: Matt Ranostay <mranostay@ti.com> >> Signed-off-by: Achal Verma <a-verma1@ti.com> >> --- >> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi >> index ef352e32f19d..5e62b431d6e8 100644 >> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi >> @@ -729,7 +729,7 @@ pcie1_rc: pcie@2910000 { >> device_type = "pci"; >> ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; >> max-link-speed = <3>; >> - num-lanes = <4>; >> + num-lanes = <2>; >> power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; >> clocks = <&k3_clks 240 6>; >> clock-names = "fck"; >> @@ -757,7 +757,7 @@ pcie1_ep: pcie-ep@2910000 { >> interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; >> ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; >> max-link-speed = <3>; >> - num-lanes = <4>; >> + num-lanes = <2>; >> power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; >> clocks = <&k3_clks 240 6>; >> clock-names = "fck"; >
On 11:52-20230516, Achal Verma wrote: > From: Matt Ranostay <mranostay@ti.com> > > J7200 has a limited 2x support for PCIe, and the properties should be > updated as such. > What commit does this fix? > Signed-off-by: Matt Ranostay <mranostay@ti.com> > Signed-off-by: Achal Verma <a-verma1@ti.com> > --- > arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi > index ef352e32f19d..5e62b431d6e8 100644 > --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi > @@ -729,7 +729,7 @@ pcie1_rc: pcie@2910000 { > device_type = "pci"; > ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; > max-link-speed = <3>; > - num-lanes = <4>; > + num-lanes = <2>; > power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; > clocks = <&k3_clks 240 6>; > clock-names = "fck"; > @@ -757,7 +757,7 @@ pcie1_ep: pcie-ep@2910000 { > interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; > ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; > max-link-speed = <3>; > - num-lanes = <4>; > + num-lanes = <2>; > power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; > clocks = <&k3_clks 240 6>; > clock-names = "fck"; > -- > 2.25.1 >
On 5/16/2023 6:43 PM, Nishanth Menon wrote: > On 11:52-20230516, Achal Verma wrote: >> From: Matt Ranostay <mranostay@ti.com> >> >> J7200 has a limited 2x support for PCIe, and the properties should be >> updated as such. >> > > What commit does this fix? This patch is a mistake. J7200 PCIe has 4 lanes, and this patch should be dropped. Regards, Achal Verma > >> Signed-off-by: Matt Ranostay <mranostay@ti.com> >> Signed-off-by: Achal Verma <a-verma1@ti.com> >> --- >> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi >> index ef352e32f19d..5e62b431d6e8 100644 >> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi >> @@ -729,7 +729,7 @@ pcie1_rc: pcie@2910000 { >> device_type = "pci"; >> ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; >> max-link-speed = <3>; >> - num-lanes = <4>; >> + num-lanes = <2>; >> power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; >> clocks = <&k3_clks 240 6>; >> clock-names = "fck"; >> @@ -757,7 +757,7 @@ pcie1_ep: pcie-ep@2910000 { >> interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; >> ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; >> max-link-speed = <3>; >> - num-lanes = <4>; >> + num-lanes = <2>; >> power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; >> clocks = <&k3_clks 240 6>; >> clock-names = "fck"; >> -- >> 2.25.1 >> > >
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index ef352e32f19d..5e62b431d6e8 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -729,7 +729,7 @@ pcie1_rc: pcie@2910000 { device_type = "pci"; ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; max-link-speed = <3>; - num-lanes = <4>; + num-lanes = <2>; power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 240 6>; clock-names = "fck"; @@ -757,7 +757,7 @@ pcie1_ep: pcie-ep@2910000 { interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; max-link-speed = <3>; - num-lanes = <4>; + num-lanes = <2>; power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 240 6>; clock-names = "fck";