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From: Komal Bajaj <quic_kbajaj@quicinc.com>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
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Conor Dooley <conor+dt@kernel.org>
Cc: Komal Bajaj <quic_kbajaj@quicinc.com>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Subject: [PATCH v3 09/10] arm64: dts: qcom: qdu1000: Add
LLCC/system-cache-controller
Date: Fri, 12 May 2023 17:51:33 +0530
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| Series |
soc: qcom: llcc: Add support for QDU1000/QRU1000
|
|
Commit Message
Komal Bajaj
May 12, 2023, 12:21 p.m. UTC
Add a DT node for Last level cache (aka. system cache) controller
which provides control over the last level cache present on QDU1000
and QRU1000 SoCs.
Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
---
arch/arm64/boot/dts/qcom/qdu1000.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
--
2.17.1
Comments
On 12/05/2023 14:21, Komal Bajaj wrote: > Add a DT node for Last level cache (aka. system cache) controller > which provides control over the last level cache present on QDU1000 > and QRU1000 SoCs. > Must be squashed. It's difficult to spot the changes against original code. Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index ff21e7a6b312..3c557ca27500 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1322,6 +1322,22 @@ #interconnect-cells = <2>; }; + system-cache-controller@19200000 { + compatible = "qcom,qdu1000-llcc"; + reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, + <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, + <0 0x19a00000 0 0x80000>, <0 0x19b00000 0 0x80000>, + <0 0x19e00000 0 0x80000>, <0 0x19f00000 0 0x80000>, + <0 0x1a200000 0 0x80000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc4_base", "llcc5_base", + "llcc6_base", "llcc7_base", "llcc_broadcast_base"; + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + + nvmem-cell-names = "multi_chan_ddr"; + nvmem-cells = <&multi_chan_ddr>; + }; + qfprom: efuse@221c8000 { compatible = "qcom,qdu1000-qfprom", "qcom,qfprom"; reg = <0 0x221c8000 0 0x1000>;