Message ID | 20230512022036.97987-8-xingyu.wu@starfivetech.com |
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State | New |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id h9-20020a170902f54900b001a1abc91952si3013130plf.194.2023.05.11.19.41.23; Thu, 11 May 2023 19:41:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239829AbjELCWn convert rfc822-to-8bit (ORCPT <rfc822;peekingduck44@gmail.com> + 99 others); Thu, 11 May 2023 22:22:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239784AbjELCWX (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Thu, 11 May 2023 22:22:23 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BA0DE5BA9; Thu, 11 May 2023 19:22:20 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 36DD824E290; Fri, 12 May 2023 10:22:19 +0800 (CST) Received: from EXMBX061.cuchost.com (172.16.6.61) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 12 May 2023 10:22:19 +0800 Received: from localhost.localdomain (113.72.146.187) by EXMBX061.cuchost.com (172.16.6.61) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 12 May 2023 10:22:18 +0800 From: Xingyu Wu <xingyu.wu@starfivetech.com> To: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, "Michael Turquette" <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Philipp Zabel <p.zabel@pengutronix.de>, Conor Dooley <conor@kernel.org>, "Emil Renner Berthing" <kernel@esmil.dk> CC: Rob Herring <robh+dt@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Hal Feng <hal.feng@starfivetech.com>, Xingyu Wu <xingyu.wu@starfivetech.com>, William Qiu <william.qiu@starfivetech.com>, <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org> Subject: [PATCH v4 7/7] riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node Date: Fri, 12 May 2023 10:20:36 +0800 Message-ID: <20230512022036.97987-8-xingyu.wu@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230512022036.97987-1-xingyu.wu@starfivetech.com> References: <20230512022036.97987-1-xingyu.wu@starfivetech.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [113.72.146.187] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX061.cuchost.com (172.16.6.61) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765654445953475317?= X-GMAIL-MSGID: =?utf-8?q?1765654445953475317?= |
Series |
Add PLL clocks driver and syscon for StarFive JH7110 SoC
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Commit Message
Xingyu Wu
May 12, 2023, 2:20 a.m. UTC
Add the PLL clock node for the Starfive JH7110 SoC and
modify the SYSCRG node to add PLL clocks input.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
Comments
On 12/05/2023 04:20, Xingyu Wu wrote: > Add the PLL clock node for the Starfive JH7110 SoC and > modify the SYSCRG node to add PLL clocks input. > @@ -465,6 +469,12 @@ syscrg: clock-controller@13020000 { > sys_syscon: syscon@13030000 { > compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; > reg = <0x0 0x13030000 0x0 0x1000>; > + > + pllclk: clock-controller { > + compatible = "starfive,jh7110-pll"; > + clocks = <&osc>; > + #clock-cells = <1>; This should be part of previous patch. You just added that node. Don't add half of devices but entire device. Best regards, Krzysztof
On 2023/5/12 14:37, Krzysztof Kozlowski wrote: > On 12/05/2023 04:20, Xingyu Wu wrote: >> Add the PLL clock node for the Starfive JH7110 SoC and >> modify the SYSCRG node to add PLL clocks input. > > >> @@ -465,6 +469,12 @@ syscrg: clock-controller@13020000 { >> sys_syscon: syscon@13030000 { >> compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; >> reg = <0x0 0x13030000 0x0 0x1000>; >> + >> + pllclk: clock-controller { >> + compatible = "starfive,jh7110-pll"; >> + clocks = <&osc>; >> + #clock-cells = <1>; > > This should be part of previous patch. You just added that node. Don't > add half of devices but entire device. > So do I merge the patch 6 and patch 7 into one patch and add syscon and clock-controller together? Best regards, Xingyu Wu
On 12/05/2023 09:15, Xingyu Wu wrote: > On 2023/5/12 14:37, Krzysztof Kozlowski wrote: >> On 12/05/2023 04:20, Xingyu Wu wrote: >>> Add the PLL clock node for the Starfive JH7110 SoC and >>> modify the SYSCRG node to add PLL clocks input. >> >> >>> @@ -465,6 +469,12 @@ syscrg: clock-controller@13020000 { >>> sys_syscon: syscon@13030000 { >>> compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; >>> reg = <0x0 0x13030000 0x0 0x1000>; >>> + >>> + pllclk: clock-controller { >>> + compatible = "starfive,jh7110-pll"; >>> + clocks = <&osc>; >>> + #clock-cells = <1>; >> >> This should be part of previous patch. You just added that node. Don't >> add half of devices but entire device. >> > > So do I merge the patch 6 and patch 7 into one patch and add syscon and > clock-controller together? I am okay with adding users of clocks in separate patch, but the clock controller - so part of SYS - should be added when adding SYS. Best regards, Krzysztof
On 2023/5/12 15:22, Krzysztof Kozlowski wrote: > On 12/05/2023 09:15, Xingyu Wu wrote: >> On 2023/5/12 14:37, Krzysztof Kozlowski wrote: >>> On 12/05/2023 04:20, Xingyu Wu wrote: >>>> Add the PLL clock node for the Starfive JH7110 SoC and >>>> modify the SYSCRG node to add PLL clocks input. >>> >>> >>>> @@ -465,6 +469,12 @@ syscrg: clock-controller@13020000 { >>>> sys_syscon: syscon@13030000 { >>>> compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; >>>> reg = <0x0 0x13030000 0x0 0x1000>; >>>> + >>>> + pllclk: clock-controller { >>>> + compatible = "starfive,jh7110-pll"; >>>> + clocks = <&osc>; >>>> + #clock-cells = <1>; >>> >>> This should be part of previous patch. You just added that node. Don't >>> add half of devices but entire device. >>> >> >> So do I merge the patch 6 and patch 7 into one patch and add syscon and >> clock-controller together? > > I am okay with adding users of clocks in separate patch, but the clock > controller - so part of SYS - should be added when adding SYS. > Got it. Thanks. Best regards, Xingyu Wu
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index fa27fd4169a8..cdfd036a0e6c 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -452,12 +452,16 @@ syscrg: clock-controller@13020000 { <&gmac1_rgmii_rxin>, <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, - <&tdm_ext>, <&mclk_ext>; + <&tdm_ext>, <&mclk_ext>, + <&pllclk JH7110_CLK_PLL0_OUT>, + <&pllclk JH7110_CLK_PLL1_OUT>, + <&pllclk JH7110_CLK_PLL2_OUT>; clock-names = "osc", "gmac1_rmii_refin", "gmac1_rgmii_rxin", "i2stx_bclk_ext", "i2stx_lrck_ext", "i2srx_bclk_ext", "i2srx_lrck_ext", - "tdm_ext", "mclk_ext"; + "tdm_ext", "mclk_ext", + "pll0_out", "pll1_out", "pll2_out"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -465,6 +469,12 @@ syscrg: clock-controller@13020000 { sys_syscon: syscon@13030000 { compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; reg = <0x0 0x13030000 0x0 0x1000>; + + pllclk: clock-controller { + compatible = "starfive,jh7110-pll"; + clocks = <&osc>; + #clock-cells = <1>; + }; }; sysgpio: pinctrl@13040000 {