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[v2,1/5] riscv: Add the T-HEAD SoC family Kconfig option
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Commit Message
李扬韬
May 10, 2023, 8:44 p.m. UTC
From: Jisheng Zhang <jszhang@kernel.org> The first SoC in the T-HEAD series is light(a.k.a th1520), containing quad T-HEAD C910 cores. Cc: Icenowy Zheng <uwu@icenowy.me> Cc: Wei Fu <wefu@redhat.com> Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Signed-off-by: Yangtao Li <frank.li@vivo.com> --- arch/riscv/Kconfig.socs | 6 ++++++ 1 file changed, 6 insertions(+)
Comments
HI Yangtao: On 04:44 Thu 11 May , Yangtao Li wrote: > From: Jisheng Zhang <jszhang@kernel.org> > > The first SoC in the T-HEAD series is light(a.k.a th1520), containing > quad T-HEAD C910 cores. > > Cc: Icenowy Zheng <uwu@icenowy.me> > Cc: Wei Fu <wefu@redhat.com> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > Signed-off-by: Yangtao Li <frank.li@vivo.com> > --- > arch/riscv/Kconfig.socs | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > index 1cf69f958f10..ce10a38dff37 100644 > --- a/arch/riscv/Kconfig.socs > +++ b/arch/riscv/Kconfig.socs > @@ -41,6 +41,12 @@ config ARCH_SUNXI > This enables support for Allwinner sun20i platform hardware, > including boards based on the D1 and D1s SoCs. > > +config ARCH_THEAD > + bool "T-HEAD RISC-V SoCs" > + select ERRATA_THEAD > + help > + This enables support for the RISC-V based T-HEAD SoCs. This help section is a little bit short.. better to provide more information about the T-Head's SoC series you want to cover? > + > config ARCH_VIRT > def_bool SOC_VIRT > > -- > 2.34.1 > It would be great to have a cover letter for this series plus having an overall history changes Just curious, so you've taked to Jisheng, to take over this series? and will do follow-up version bump?
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 1cf69f958f10..ce10a38dff37 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -41,6 +41,12 @@ config ARCH_SUNXI This enables support for Allwinner sun20i platform hardware, including boards based on the D1 and D1s SoCs. +config ARCH_THEAD + bool "T-HEAD RISC-V SoCs" + select ERRATA_THEAD + help + This enables support for the RISC-V based T-HEAD SoCs. + config ARCH_VIRT def_bool SOC_VIRT