diff mbox series

[v2,2/2] clk: mediatek: reset: add infra_ao reset support for MT8188

Message ID 20230505131308.27190-3-runyang.chen@mediatek.com
State New
Headers
Series Add infra_ao reset support for MT8188 Soc |

Commit Message

Runyang Chen May 5, 2023, 1:13 p.m. UTC 
  The infra_ao reset is needed for MT8188.
- Add mtk_clk_rst_desc for MT8188.
- Add register reset controller function for MT8188 infra_ao.
- Add infra_ao_idx_map for MT8188.

Signed-off-by: Runyang Chen <runyang.chen@mediatek.com>
---
 drivers/clk/mediatek/clk-mt8188-infra_ao.c | 24 ++++++++++++++++++++++
 1 file changed, 24 insertions(+)

Comments

Stephen Boyd May 10, 2023, 9:20 p.m. UTC | #1 
Quoting Runyang Chen (2023-05-05 06:13:08)
> @@ -176,9 +177,32 @@ static const struct mtk_gate infra_ao_clks[] = {
>                        "infra_ao_aes_msdcfde_0p", "top_aes_msdcfde", 18),
>  };
>  
> +static u16 infra_ao_rst_ofs[] = {

const?

> +       INFRA_RST0_SET_OFFSET,
> +       INFRA_RST1_SET_OFFSET,
> +       INFRA_RST2_SET_OFFSET,
> +       INFRA_RST3_SET_OFFSET,
> +       INFRA_RST4_SET_OFFSET,
> +};
> +
> +static u16 infra_ao_idx_map[] = {

const?

> +       [MT8188_INFRA_RST1_THERMAL_MCU_RST] = 1 * RST_NR_PER_BANK + 2,
> +       [MT8188_INFRA_RST1_THERMAL_CTRL_RST] = 1 * RST_NR_PER_BANK + 4,
> +       [MT8188_INFRA_RST3_PTP_CTRL_RST] = 3 * RST_NR_PER_BANK + 5,
> +};
> +
> +static struct mtk_clk_rst_desc infra_ao_rst_desc = {
> +       .version = MTK_RST_SET_CLR,
> +       .rst_bank_ofs = infra_ao_rst_ofs,
> +       .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
> +       .rst_idx_map = infra_ao_idx_map,
> +       .rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
> +};
> +
>  static const struct mtk_clk_desc infra_ao_desc = {
>         .clks = infra_ao_clks,
>         .num_clks = ARRAY_SIZE(infra_ao_clks),
> +       .rst_desc = &infra_ao_rst_desc,
>  };
Runyang Chen May 25, 2023, 6:46 a.m. UTC | #2 
On Wed, 2023-05-10 at 14:20 -0700, Stephen Boyd wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> Quoting Runyang Chen (2023-05-05 06:13:08)
> > @@ -176,9 +177,32 @@ static const struct mtk_gate infra_ao_clks[] =
> > {
> >                        "infra_ao_aes_msdcfde_0p",
> > "top_aes_msdcfde", 18),
> >  };
> > 
> > +static u16 infra_ao_rst_ofs[] = {
> 
> const?

The infra_ao_rst_ofs and infra_ao_idx_map will be modified by the reset
controller driver, so it could not be constified. And previous code did
not set it as const.
> 
> > +       INFRA_RST0_SET_OFFSET,
> > +       INFRA_RST1_SET_OFFSET,
> > +       INFRA_RST2_SET_OFFSET,
> > +       INFRA_RST3_SET_OFFSET,
> > +       INFRA_RST4_SET_OFFSET,
> > +};
> > +
> > +static u16 infra_ao_idx_map[] = {
> 
> const?
> 
> > +       [MT8188_INFRA_RST1_THERMAL_MCU_RST] = 1 * RST_NR_PER_BANK +
> > 2,
> > +       [MT8188_INFRA_RST1_THERMAL_CTRL_RST] = 1 * RST_NR_PER_BANK
> > + 4,
> > +       [MT8188_INFRA_RST3_PTP_CTRL_RST] = 3 * RST_NR_PER_BANK + 5,
> > +};
> > +
> > +static struct mtk_clk_rst_desc infra_ao_rst_desc = {

infra_ao_rst_desc will be constified at V4.

> > +       .version = MTK_RST_SET_CLR,
> > +       .rst_bank_ofs = infra_ao_rst_ofs,
> > +       .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
> > +       .rst_idx_map = infra_ao_idx_map,
> > +       .rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
> > +};
> > +
> >  static const struct mtk_clk_desc infra_ao_desc = {
> >         .clks = infra_ao_clks,
> >         .num_clks = ARRAY_SIZE(infra_ao_clks),
> > +       .rst_desc = &infra_ao_rst_desc,
> >  };
Runyang Chen May 25, 2023, 7:12 a.m. UTC | #3 
On Wed, 2023-05-10 at 14:20 -0700, Stephen Boyd wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> Quoting Runyang Chen (2023-05-05 06:13:08)
> > @@ -176,9 +177,32 @@ static const struct mtk_gate infra_ao_clks[] =
> > {
> >                        "infra_ao_aes_msdcfde_0p",
> > "top_aes_msdcfde", 18),
> >  };
> > 
> > +static u16 infra_ao_rst_ofs[] = {
> 
> const?

The infra_ao_rst_ofs and infra_ao_idx_map will be modified by the reset
controller driver, so it could not be constified. And previous code did
not set it as const.

> 
> > +       INFRA_RST0_SET_OFFSET,
> > +       INFRA_RST1_SET_OFFSET,
> > +       INFRA_RST2_SET_OFFSET,
> > +       INFRA_RST3_SET_OFFSET,
> > +       INFRA_RST4_SET_OFFSET,
> > +};
> > +
> > +static u16 infra_ao_idx_map[] = {
> 
> const?
> 
> > +       [MT8188_INFRA_RST1_THERMAL_MCU_RST] = 1 * RST_NR_PER_BANK +
> > 2,
> > +       [MT8188_INFRA_RST1_THERMAL_CTRL_RST] = 1 * RST_NR_PER_BANK
> > + 4,
> > +       [MT8188_INFRA_RST3_PTP_CTRL_RST] = 3 * RST_NR_PER_BANK + 5,
> > +};
> > +
> > +static struct mtk_clk_rst_desc infra_ao_rst_desc = {

infra_ao_rst_desc will be constified at V4.

> > +       .version = MTK_RST_SET_CLR,
> > +       .rst_bank_ofs = infra_ao_rst_ofs,
> > +       .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
> > +       .rst_idx_map = infra_ao_idx_map,
> > +       .rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
> > +};
> > +
> >  static const struct mtk_clk_desc infra_ao_desc = {
> >         .clks = infra_ao_clks,
> >         .num_clks = ARRAY_SIZE(infra_ao_clks),
> > +       .rst_desc = &infra_ao_rst_desc,
> >  };
diff mbox series

Patch

diff --git a/drivers/clk/mediatek/clk-mt8188-infra_ao.c b/drivers/clk/mediatek/clk-mt8188-infra_ao.c
index 91c35db40b4e..1d4b27ba06be 100644
--- a/drivers/clk/mediatek/clk-mt8188-infra_ao.c
+++ b/drivers/clk/mediatek/clk-mt8188-infra_ao.c
@@ -5,6 +5,7 @@ 
  */
 
 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
+#include <dt-bindings/reset/mt8188-resets.h>
 #include <linux/clk-provider.h>
 #include <linux/platform_device.h>
 
@@ -176,9 +177,32 @@  static const struct mtk_gate infra_ao_clks[] = {
 		       "infra_ao_aes_msdcfde_0p", "top_aes_msdcfde", 18),
 };
 
+static u16 infra_ao_rst_ofs[] = {
+	INFRA_RST0_SET_OFFSET,
+	INFRA_RST1_SET_OFFSET,
+	INFRA_RST2_SET_OFFSET,
+	INFRA_RST3_SET_OFFSET,
+	INFRA_RST4_SET_OFFSET,
+};
+
+static u16 infra_ao_idx_map[] = {
+	[MT8188_INFRA_RST1_THERMAL_MCU_RST] = 1 * RST_NR_PER_BANK + 2,
+	[MT8188_INFRA_RST1_THERMAL_CTRL_RST] = 1 * RST_NR_PER_BANK + 4,
+	[MT8188_INFRA_RST3_PTP_CTRL_RST] = 3 * RST_NR_PER_BANK + 5,
+};
+
+static struct mtk_clk_rst_desc infra_ao_rst_desc = {
+	.version = MTK_RST_SET_CLR,
+	.rst_bank_ofs = infra_ao_rst_ofs,
+	.rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
+	.rst_idx_map = infra_ao_idx_map,
+	.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
+};
+
 static const struct mtk_clk_desc infra_ao_desc = {
 	.clks = infra_ao_clks,
 	.num_clks = ARRAY_SIZE(infra_ao_clks),
+	.rst_desc = &infra_ao_rst_desc,
 };
 
 static const struct of_device_id of_match_clk_mt8188_infra_ao[] = {