Message ID | 20230508115237.216337-4-sunilvl@ventanamicro.com |
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State | New |
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([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.53.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:53:19 -0700 (PDT) From: Sunil V L <sunilvl@ventanamicro.com> To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet <corbet@lwn.net>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, "Rafael J . Wysocki" <rafael@kernel.org>, Len Brown <lenb@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Weili Qian <qianweili@huawei.com>, Zhou Wang <wangzhou1@hisilicon.com>, Herbert Xu <herbert@gondor.apana.org.au>, "David S . Miller" <davem@davemloft.net>, Marc Zyngier <maz@kernel.org>, Maximilian Luz <luzmaximilian@gmail.com>, Hans de Goede <hdegoede@redhat.com>, Mark Gross <markgross@kernel.org>, Nathan Chancellor <nathan@kernel.org>, Nick Desaulniers <ndesaulniers@google.com>, Tom Rix <trix@redhat.com>, Sunil V L <sunilvl@ventanamicro.com> Subject: [PATCH V5 03/21] crypto: hisilicon/qm: Fix to enable build with RISC-V clang Date: Mon, 8 May 2023 17:22:19 +0530 Message-Id: <20230508115237.216337-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765327763747215118?= X-GMAIL-MSGID: =?utf-8?q?1765327763747215118?= |
Series |
Add basic ACPI support for RISC-V
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Commit Message
Sunil V L
May 8, 2023, 11:52 a.m. UTC
With CONFIG_ACPI enabled for RISC-V, this driver gets enabled in allmodconfig build. However, build fails with clang and below error is seen. drivers/crypto/hisilicon/qm.c:627:10: error: invalid output constraint '+Q' in asm "+Q" (*((char __iomem *)fun_base)) ^ This is expected error with clang due to the way it is designed. To fix this issue, move arm64 assembly code under #if. Link: https://github.com/ClangBuiltLinux/linux/issues/999 Signed-off-by: Nathan Chancellor <nathan@kernel.org> [sunilvl@ventanamicro.com: Moved tmp0 and tmp1 into the #if] Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> --- drivers/crypto/hisilicon/qm.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-)
Comments
On Mon, May 08, 2023 at 05:22:19PM +0530, Sunil V L wrote: > With CONFIG_ACPI enabled for RISC-V, this driver gets enabled in > allmodconfig build. However, build fails with clang and below > error is seen. > > drivers/crypto/hisilicon/qm.c:627:10: error: invalid output constraint '+Q' in asm > "+Q" (*((char __iomem *)fun_base)) > ^ > This is expected error with clang due to the way it is designed. > > To fix this issue, move arm64 assembly code under #if. > > Link: https://github.com/ClangBuiltLinux/linux/issues/999 > Signed-off-by: Nathan Chancellor <nathan@kernel.org> > [sunilvl@ventanamicro.com: Moved tmp0 and tmp1 into the #if] > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> > --- > drivers/crypto/hisilicon/qm.c | 13 +++++++------ > 1 file changed, 7 insertions(+), 6 deletions(-) > > diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c > index ad0c042b5e66..2eaeaac2e246 100644 > --- a/drivers/crypto/hisilicon/qm.c > +++ b/drivers/crypto/hisilicon/qm.c > @@ -610,13 +610,9 @@ EXPORT_SYMBOL_GPL(hisi_qm_wait_mb_ready); > static void qm_mb_write(struct hisi_qm *qm, const void *src) > { > void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE; > - unsigned long tmp0 = 0, tmp1 = 0; > > - if (!IS_ENABLED(CONFIG_ARM64)) { > - memcpy_toio(fun_base, src, 16); > - dma_wmb(); > - return; > - } Please leave this bit as it stands. > +#if IS_ENABLED(CONFIG_ARM64) > + unsigned long tmp0 = 0, tmp1 = 0; > > asm volatile("ldp %0, %1, %3\n" > "stp %0, %1, %2\n" > @@ -626,6 +622,11 @@ static void qm_mb_write(struct hisi_qm *qm, const void *src) > "+Q" (*((char __iomem *)fun_base)) > : "Q" (*((char *)src)) > : "memory"); And simply add the ifdef around the assembly. Thanks,
On Tue, May 09, 2023 at 10:17:45AM +0800, Herbert Xu wrote: > On Mon, May 08, 2023 at 05:22:19PM +0530, Sunil V L wrote: > > With CONFIG_ACPI enabled for RISC-V, this driver gets enabled in > > allmodconfig build. However, build fails with clang and below > > error is seen. > > > > drivers/crypto/hisilicon/qm.c:627:10: error: invalid output constraint '+Q' in asm > > "+Q" (*((char __iomem *)fun_base)) > > ^ > > This is expected error with clang due to the way it is designed. > > > > To fix this issue, move arm64 assembly code under #if. > > > > Link: https://github.com/ClangBuiltLinux/linux/issues/999 > > Signed-off-by: Nathan Chancellor <nathan@kernel.org> > > [sunilvl@ventanamicro.com: Moved tmp0 and tmp1 into the #if] > > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> > > --- > > drivers/crypto/hisilicon/qm.c | 13 +++++++------ > > 1 file changed, 7 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c > > index ad0c042b5e66..2eaeaac2e246 100644 > > --- a/drivers/crypto/hisilicon/qm.c > > +++ b/drivers/crypto/hisilicon/qm.c > > @@ -610,13 +610,9 @@ EXPORT_SYMBOL_GPL(hisi_qm_wait_mb_ready); > > static void qm_mb_write(struct hisi_qm *qm, const void *src) > > { > > void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE; > > - unsigned long tmp0 = 0, tmp1 = 0; > > > > - if (!IS_ENABLED(CONFIG_ARM64)) { > > - memcpy_toio(fun_base, src, 16); > > - dma_wmb(); > > - return; > > - } > > Please leave this bit as it stands. > > > +#if IS_ENABLED(CONFIG_ARM64) > > + unsigned long tmp0 = 0, tmp1 = 0; > > > > asm volatile("ldp %0, %1, %3\n" > > "stp %0, %1, %2\n" > > @@ -626,6 +622,11 @@ static void qm_mb_write(struct hisi_qm *qm, const void *src) > > "+Q" (*((char __iomem *)fun_base)) > > : "Q" (*((char *)src)) > > : "memory"); > > And simply add the ifdef around the assembly. > Sure, Herbert. Thanks! Sunil
diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index ad0c042b5e66..2eaeaac2e246 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -610,13 +610,9 @@ EXPORT_SYMBOL_GPL(hisi_qm_wait_mb_ready); static void qm_mb_write(struct hisi_qm *qm, const void *src) { void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE; - unsigned long tmp0 = 0, tmp1 = 0; - if (!IS_ENABLED(CONFIG_ARM64)) { - memcpy_toio(fun_base, src, 16); - dma_wmb(); - return; - } +#if IS_ENABLED(CONFIG_ARM64) + unsigned long tmp0 = 0, tmp1 = 0; asm volatile("ldp %0, %1, %3\n" "stp %0, %1, %2\n" @@ -626,6 +622,11 @@ static void qm_mb_write(struct hisi_qm *qm, const void *src) "+Q" (*((char __iomem *)fun_base)) : "Q" (*((char *)src)) : "memory"); +#else + memcpy_toio(fun_base, src, 16); + dma_wmb(); +#endif + } static int qm_mb_nolock(struct hisi_qm *qm, struct qm_mailbox *mailbox)