diff mbox series

drm/msm/dpu: Set DPU_DATA_HCTL_EN for in INTF_SC7180_MASK

Message ID 20230508-topic-hctl_en-v1-1-0f8b5df60ed5@linaro.org
State New
Headers
Series drm/msm/dpu: Set DPU_DATA_HCTL_EN for in INTF_SC7180_MASK |

Commit Message

Konrad Dybcio May 8, 2023, 10:29 a.m. UTC 
  DPU5 and newer targets enable this unconditionally. Move it from the
SC7280 mask to the SC7180 one.

Fixes: 7bdc0c4b8126 ("msm:disp:dpu1: add support for display for SC7180 target")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Depends on:
https://lore.kernel.org/linux-arm-msm/20230405-add-dsc-support-v2-0-1072c70e9786@quicinc.com/
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)


---
base-commit: c47189dee0decd9ecc1e65ae376ad6d4b0b7f1f2
change-id: 20230508-topic-hctl_en-3abb999a6c99

Best regards,

Comments

Marijn Suijten May 8, 2023, 10:57 a.m. UTC | #1 
On 2023-05-08 12:29:32, Konrad Dybcio wrote:
> DPU5 and newer targets enable this unconditionally. Move it from the
> SC7280 mask to the SC7180 one.
> 
> Fixes: 7bdc0c4b8126 ("msm:disp:dpu1: add support for display for SC7180 target")

The flag only exists since 591e34a091d17 ("drm/msm/disp/dpu1: add
support for display for SC7280 target"), and I don't know how bad it is
if it was lacking when SC7180 was added?

> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>

I wonder if this needs any Reported-by/Suggested-by, given that I found
the DATA_COMPRESS discrepancy for your SM6375 patch (which was using
SC7280 to have the HCTL mask) and Dmitry pointing out that HCTL needs to
be in SC7180 entirely.

Fortunately none of this affects cmdmode :)

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>

> ---
> Depends on:
> https://lore.kernel.org/linux-arm-msm/20230405-add-dsc-support-v2-0-1072c70e9786@quicinc.com/
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 27420fc863d6..7ea8fd69d5fd 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -98,9 +98,12 @@
>  #define INTF_SDM845_MASK (0)
>  
>  #define INTF_SC7180_MASK \
> -	(BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) | BIT(DPU_INTF_STATUS_SUPPORTED))
> +	(BIT(DPU_INTF_INPUT_CTRL) | \
> +	 BIT(DPU_INTF_TE) | \
> +	 BIT(DPU_INTF_STATUS_SUPPORTED) | \
> +	 BIT(DPU_DATA_HCTL_EN))
>  
> -#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) | BIT(DPU_INTF_DATA_COMPRESS)
> +#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_INTF_DATA_COMPRESS)
>  
>  #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
>  			 BIT(DPU_WB_UBWC) | \
> 
> ---
> base-commit: c47189dee0decd9ecc1e65ae376ad6d4b0b7f1f2
> change-id: 20230508-topic-hctl_en-3abb999a6c99
> 
> Best regards,
> -- 
> Konrad Dybcio <konrad.dybcio@linaro.org>
>
Dmitry Baryshkov May 8, 2023, 11:26 a.m. UTC | #2 
On 08/05/2023 13:57, Marijn Suijten wrote:
> On 2023-05-08 12:29:32, Konrad Dybcio wrote:
>> DPU5 and newer targets enable this unconditionally. Move it from the
>> SC7280 mask to the SC7180 one.
>>
>> Fixes: 7bdc0c4b8126 ("msm:disp:dpu1: add support for display for SC7180 target")
> 
> The flag only exists since 591e34a091d17 ("drm/msm/disp/dpu1: add
> support for display for SC7280 target"), and I don't know how bad it is
> if it was lacking when SC7180 was added?

I think 591e34a091d1 ("drm/msm/disp/dpu1: add support for display for 
SC7280 target") or 7e6ee55320f0 ("drm/msm/disp/dpu1: enable DATA_HCTL_EN 
for sc7280 target") would be more appropriate here.

With that in place:

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>


> 
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> 
> I wonder if this needs any Reported-by/Suggested-by, given that I found
> the DATA_COMPRESS discrepancy for your SM6375 patch (which was using
> SC7280 to have the HCTL mask) and Dmitry pointing out that HCTL needs to
> be in SC7180 entirely.
> 
> Fortunately none of this affects cmdmode :)
> 
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> 
>> ---
>> Depends on:
>> https://lore.kernel.org/linux-arm-msm/20230405-add-dsc-support-v2-0-1072c70e9786@quicinc.com/
>> ---
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 7 +++++--
>>   1 file changed, 5 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index 27420fc863d6..7ea8fd69d5fd 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -98,9 +98,12 @@
>>   #define INTF_SDM845_MASK (0)
>>   
>>   #define INTF_SC7180_MASK \
>> -	(BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) | BIT(DPU_INTF_STATUS_SUPPORTED))
>> +	(BIT(DPU_INTF_INPUT_CTRL) | \
>> +	 BIT(DPU_INTF_TE) | \
>> +	 BIT(DPU_INTF_STATUS_SUPPORTED) | \
>> +	 BIT(DPU_DATA_HCTL_EN))
>>   
>> -#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) | BIT(DPU_INTF_DATA_COMPRESS)
>> +#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_INTF_DATA_COMPRESS)
>>   
>>   #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
>>   			 BIT(DPU_WB_UBWC) | \
>>
>> ---
>> base-commit: c47189dee0decd9ecc1e65ae376ad6d4b0b7f1f2
>> change-id: 20230508-topic-hctl_en-3abb999a6c99
>>
>> Best regards,
>> -- 
>> Konrad Dybcio <konrad.dybcio@linaro.org>
>>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 27420fc863d6..7ea8fd69d5fd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -98,9 +98,12 @@ 
 #define INTF_SDM845_MASK (0)
 
 #define INTF_SC7180_MASK \
-	(BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) | BIT(DPU_INTF_STATUS_SUPPORTED))
+	(BIT(DPU_INTF_INPUT_CTRL) | \
+	 BIT(DPU_INTF_TE) | \
+	 BIT(DPU_INTF_STATUS_SUPPORTED) | \
+	 BIT(DPU_DATA_HCTL_EN))
 
-#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) | BIT(DPU_INTF_DATA_COMPRESS)
+#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_INTF_DATA_COMPRESS)
 
 #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
 			 BIT(DPU_WB_UBWC) | \