Message ID | 20230507182304.2934-2-jszhang@kernel.org |
---|---|
State | New |
Headers |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id jj3-20020a170903048300b001a66c437b2esi6210682plb.20.2023.05.07.11.35.02; Sun, 07 May 2023 11:35:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=iI2gauWX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231415AbjEGSeU (ORCPT <rfc822;baris.duru.linux@gmail.com> + 99 others); Sun, 7 May 2023 14:34:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229460AbjEGSeR (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Sun, 7 May 2023 14:34:17 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 024D36E82; Sun, 7 May 2023 11:34:17 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8C0C460FB1; Sun, 7 May 2023 18:34:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6F72FC433A1; Sun, 7 May 2023 18:34:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683484456; bh=BANIf+ASt30mN5iS/NWLlkQ2ov0wGoxCBBMNfEgEvLk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iI2gauWXX+FpvZGeuZivJ5XIu/c/TN8lfj5WAK9mc72mvIoGhJH2S9uYQDOJymWlE LulXx6JEDOKWhOmWkm7ja3YdWQHbNavQi1lD0RN7dvxG8QSXcuyUX0ecMFHWUJ8HTO OoN3SPK/P+sGNQHeOzRFx4kXJmF/y3Gr2muWMdu2FKCJWiJSK0jsnib5zH5siuLnOO 7HITT5jeGH4riYtTIBC35hmL1GsO0GU0ZlnKYhCbOJcrp/xXMa7bgArhNC9LnfHqXh tNUJe8EbpWaj8kXhIthunrRBkly54fbXcirV3z//8Z9Ol1HTI4LTT7FyVxoiJxahnq iw3IQNL5k9ZwA== From: Jisheng Zhang <jszhang@kernel.org> To: Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu> Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren <guoren@kernel.org> Subject: [PATCH 1/5] irqchip/sifive-plic: Support T-HEAD's C910 PLIC Date: Mon, 8 May 2023 02:23:00 +0800 Message-Id: <20230507182304.2934-2-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230507182304.2934-1-jszhang@kernel.org> References: <20230507182304.2934-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765261458228691173?= X-GMAIL-MSGID: =?utf-8?q?1765261458228691173?= |
Series |
Add Sipeed Lichee Pi 4A RISC-V board support
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Commit Message
Jisheng Zhang
May 7, 2023, 6:23 p.m. UTC
The T-HEAD's C910 PLIC still needs the delegation bit settingto allow
access from S-mode, but it doesn't need the edge quirk.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 4 ++++
drivers/irqchip/irq-sifive-plic.c | 1 +
2 files changed, 5 insertions(+)
Comments
Hey Jisheng, On Mon, May 08, 2023 at 02:23:00AM +0800, Jisheng Zhang wrote: > The T-HEAD's C910 PLIC still needs the delegation bit settingto allow > access from S-mode, but it doesn't need the edge quirk. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 4 ++++ > drivers/irqchip/irq-sifive-plic.c | 1 + dt-bindings changes need to be in their own patch. > 2 files changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > index f75736a061af..64b43a3c3748 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > @@ -62,6 +62,10 @@ properties: > - starfive,jh7110-plic > - canaan,k210-plic > - const: sifive,plic-1.0.0 > + - items: > + - enum: > + - thead,light-plic If "light" is a code name, but "TH1520" is what this is known as to the wider world, I think we should use thead,th1520-plic here. Thanks, Conor. > + - const: thead,c910-plic > - items: > - enum: > - allwinner,sun20i-d1-plic > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c > index e1484905b7bd..71afa2a584d9 100644 > --- a/drivers/irqchip/irq-sifive-plic.c > +++ b/drivers/irqchip/irq-sifive-plic.c > @@ -569,6 +569,7 @@ static int __init plic_init(struct device_node *node, > } > > IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); > +IRQCHIP_DECLARE(thead_c910_plic, "thead,c910-plic", plic_init); > IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */ > > static int __init plic_edge_init(struct device_node *node, > -- > 2.40.0 >
在 2023-05-08星期一的 02:23 +0800,Jisheng Zhang写道: > The T-HEAD's C910 PLIC still needs the delegation bit settingto allow > access from S-mode, but it doesn't need the edge quirk. No, the PLIC controller seems to be the same between C906 and C910, which has level/edge selectable via external signal. See openc906 and openc910 repositories, especially the documents with it: 玄铁C9{06,10}集成手册.pdf . In addition, such problem won't arise when the system uses only level- triggered interrupts. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 4 > ++++ > drivers/irqchip/irq-sifive-plic.c | 1 + > 2 files changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/interrupt- > controller/sifive,plic-1.0.0.yaml > b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic- > 1.0.0.yaml > index f75736a061af..64b43a3c3748 100644 > --- a/Documentation/devicetree/bindings/interrupt- > controller/sifive,plic-1.0.0.yaml > +++ b/Documentation/devicetree/bindings/interrupt- > controller/sifive,plic-1.0.0.yaml > @@ -62,6 +62,10 @@ properties: > - starfive,jh7110-plic > - canaan,k210-plic > - const: sifive,plic-1.0.0 > + - items: > + - enum: > + - thead,light-plic > + - const: thead,c910-plic > - items: > - enum: > - allwinner,sun20i-d1-plic > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq- > sifive-plic.c > index e1484905b7bd..71afa2a584d9 100644 > --- a/drivers/irqchip/irq-sifive-plic.c > +++ b/drivers/irqchip/irq-sifive-plic.c > @@ -569,6 +569,7 @@ static int __init plic_init(struct device_node > *node, > } > > IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); > +IRQCHIP_DECLARE(thead_c910_plic, "thead,c910-plic", plic_init); > IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for > legacy systems */ > > static int __init plic_edge_init(struct device_node *node,
On Mon, May 8, 2023 at 2:34 AM Jisheng Zhang <jszhang@kernel.org> wrote: > > The T-HEAD's C910 PLIC still needs the delegation bit settingto allow > access from S-mode, but it doesn't need the edge quirk. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 4 ++++ > drivers/irqchip/irq-sifive-plic.c | 1 + > 2 files changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > index f75736a061af..64b43a3c3748 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > @@ -62,6 +62,10 @@ properties: > - starfive,jh7110-plic > - canaan,k210-plic > - const: sifive,plic-1.0.0 > + - items: > + - enum: > + - thead,light-plic > + - const: thead,c910-plic > - items: > - enum: > - allwinner,sun20i-d1-plic > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c > index e1484905b7bd..71afa2a584d9 100644 > --- a/drivers/irqchip/irq-sifive-plic.c > +++ b/drivers/irqchip/irq-sifive-plic.c > @@ -569,6 +569,7 @@ static int __init plic_init(struct device_node *node, > } > > IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); > +IRQCHIP_DECLARE(thead_c910_plic, "thead,c910-plic", plic_init); > IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */ > > static int __init plic_edge_init(struct device_node *node, > -- > 2.40.0 > opensbi needs thead,c900-plic, and we could put multi compatible name in the dts. So, it's no need here. Another question, Could we change the name of Sifive to RISC-V when "cat /proc/interrupts" ? diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index ff47bd0dec45..b5844d784bfa 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -177,7 +177,7 @@ static int plic_set_affinity(struct irq_data *d, #endif static struct irq_chip plic_edge_chip = { - .name = "SiFive PLIC", + .name = "RISC-V PLIC", .irq_enable = plic_irq_enable, .irq_disable = plic_irq_disable, .irq_ack = plic_irq_eoi, @@ -192,7 +192,7 @@ static struct irq_chip plic_edge_chip = { }; static struct irq_chip plic_chip = { - .name = "SiFive PLIC", + .name = "RISC-V PLIC", .irq_enable = plic_irq_enable, .irq_disable = plic_irq_disable, .irq_mask = plic_irq_mask,
On Mon, May 08, 2023 at 02:52:29PM +0800, Guo Ren wrote: > Another question, Could we change the name of Sifive to RISC-V when > "cat /proc/interrupts" ? Previously NAKed by Marc as it is ABI: https://lore.kernel.org/all/20511a05f39408c8ffbcc98923c4abd2@kernel.org Cheers, Conor.
On 07/05/2023 20:23, Jisheng Zhang wrote: > The T-HEAD's C910 PLIC still needs the delegation bit settingto allow > access from S-mode, but it doesn't need the edge quirk. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 4 ++++ > drivers/irqchip/irq-sifive-plic.c | 1 + Bindings are always separate patches. Please run scripts/checkpatch.pl and fix reported warnings. Best regards, Krzysztof
On Mon, May 08, 2023 at 02:52:29PM +0800, Guo Ren wrote: > On Mon, May 8, 2023 at 2:34 AM Jisheng Zhang <jszhang@kernel.org> wrote: > > > > The T-HEAD's C910 PLIC still needs the delegation bit settingto allow > > access from S-mode, but it doesn't need the edge quirk. > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > --- > > .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 4 ++++ > > drivers/irqchip/irq-sifive-plic.c | 1 + > > 2 files changed, 5 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > > index f75736a061af..64b43a3c3748 100644 > > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > > @@ -62,6 +62,10 @@ properties: > > - starfive,jh7110-plic > > - canaan,k210-plic > > - const: sifive,plic-1.0.0 > > + - items: > > + - enum: > > + - thead,light-plic > > + - const: thead,c910-plic > > - items: > > - enum: > > - allwinner,sun20i-d1-plic > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c > > index e1484905b7bd..71afa2a584d9 100644 > > --- a/drivers/irqchip/irq-sifive-plic.c > > +++ b/drivers/irqchip/irq-sifive-plic.c > > @@ -569,6 +569,7 @@ static int __init plic_init(struct device_node *node, > > } > > > > IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); > > +IRQCHIP_DECLARE(thead_c910_plic, "thead,c910-plic", plic_init); > > IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */ > > > > static int __init plic_edge_init(struct device_node *node, > > -- > > 2.40.0 > > > opensbi needs thead,c900-plic, and we could put multi compatible name > in the dts. So, it's no need here. Thanks, I misunderstood the PLIC edge quirk. This patch isn't needed any more.
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index f75736a061af..64b43a3c3748 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -62,6 +62,10 @@ properties: - starfive,jh7110-plic - canaan,k210-plic - const: sifive,plic-1.0.0 + - items: + - enum: + - thead,light-plic + - const: thead,c910-plic - items: - enum: - allwinner,sun20i-d1-plic diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index e1484905b7bd..71afa2a584d9 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -569,6 +569,7 @@ static int __init plic_init(struct device_node *node, } IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); +IRQCHIP_DECLARE(thead_c910_plic, "thead,c910-plic", plic_init); IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */ static int __init plic_edge_init(struct device_node *node,