Message ID | 20230503144706.1265672-2-u-kumar1@ti.com |
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State | New |
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Series |
arm64: dts: ti: k3-j721s2: handling subnode of msmc node
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Commit Message
Kumar, Udit
May 3, 2023, 2:47 p.m. UTC
mark atf, l3-cache and tifs node as reserved.
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 3 +++
1 file changed, 3 insertions(+)
Comments
On 03/05/2023 16:51, Nishanth Menon wrote: > On 20:17-20230503, Udit Kumar wrote: >> Mark atf, l3-cache and tifs node as reserved. > > why? (I am not reading the cover-letter for a 1 patch) And you should not have to. :) The commit msg should explain why it is useful. Best regards, Krzysztof
On 5/3/2023 8:21 PM, Nishanth Menon wrote: > On 20:17-20230503, Udit Kumar wrote: >> Mark atf, l3-cache and tifs node as reserved. > why? (I am not reading the cover-letter for a 1 patch) My bad , I should have description in patch itself. Thanks > [...] >> 2.34.1 >>
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 2dd7865f7654..791993060f44 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -14,14 +14,17 @@ msmc_ram: sram@70000000 { ranges = <0x0 0x0 0x70000000 0x400000>; atf-sram@0 { + status = "reserved"; reg = <0x0 0x20000>; }; tifs-sram@1f0000 { + status = "reserved"; reg = <0x1f0000 0x10000>; }; l3cache-sram@200000 { + status = "reserved"; reg = <0x200000 0x200000>; }; };