[v7,9/9] arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb controller
Message ID | 20230501143445.3851-10-quic_kriskura@quicinc.com |
---|---|
State | New |
Headers |
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Series |
Add multiport support for DWC3 controllers
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Commit Message
Krishna Kurapati
May 1, 2023, 2:34 p.m. UTC
There is now support for the multiport USB controller this uses so enable it. The board only has a single port hooked up (despite it being wired up to the multiport IP on the SoC). There's also a USB 2.0 mux hooked up, which by default on boot is selected to mux properly. Grab the gpio controlling that and ensure it stays in the right position so USB 2.0 continues to be routed from the external port to the SoC. Signed-off-by: Andrew Halaney <ahalaney@redhat.com> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> --- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
Comments
On 1.05.2023 16:34, Krishna Kurapati wrote: > There is now support for the multiport USB controller this uses so > enable it. > > The board only has a single port hooked up (despite it being wired up to > the multiport IP on the SoC). There's also a USB 2.0 mux hooked up, > which by default on boot is selected to mux properly. Grab the gpio > controlling that and ensure it stays in the right position so USB 2.0 > continues to be routed from the external port to the SoC. > > Signed-off-by: Andrew Halaney <ahalaney@redhat.com> > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > --- same comments as patch 8 Konrad > arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts > index 24fa449d48a6..53d47593306e 100644 > --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts > +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts > @@ -309,6 +309,19 @@ &usb_2_qmpphy0 { > status = "okay"; > }; > > +&usb_2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&usb2_en_state>; > + > + status = "okay"; > +}; > + > +&usb_2_dwc3 { > + dr_mode = "host"; > + phy-names = "usb2-port0", "usb3-port0"; > + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>; > +}; > + > &xo_board_clk { > clock-frequency = <38400000>; > }; > @@ -401,4 +414,13 @@ wake-pins { > bias-pull-up; > }; > }; > + > + usb2_en_state: usb2-en-state { > + /* TS3USB221A USB2.0 mux select */ > + pins = "gpio24"; > + function = "gpio"; > + drive-strength = <2>; > + bias-disable; > + output-low; > + }; > };
On 5/2/2023 4:37 PM, Konrad Dybcio wrote: > > > On 1.05.2023 16:34, Krishna Kurapati wrote: >> There is now support for the multiport USB controller this uses so >> enable it. >> >> The board only has a single port hooked up (despite it being wired up to >> the multiport IP on the SoC). There's also a USB 2.0 mux hooked up, >> which by default on boot is selected to mux properly. Grab the gpio >> controlling that and ensure it stays in the right position so USB 2.0 >> continues to be routed from the external port to the SoC. >> >> Signed-off-by: Andrew Halaney <ahalaney@redhat.com> >> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> >> --- > same comments as patch 8 > > Konrad Hi Konrad, Sure, will add a default value for drive-strength for this pinctrl node. Hi Andrew Halaney, I currently don't have a Ride device with me to test this change. Can you help test this patch on SA8540-Ride including (drive-strength = <2>;) property (which I believe is the default value). I can test the same on SA8295-ADP and can push the next version quickly. Regards, Krishna, >> arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++++++++++++++++++++++ >> 1 file changed, 22 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts >> index 24fa449d48a6..53d47593306e 100644 >> --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts >> +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts >> @@ -309,6 +309,19 @@ &usb_2_qmpphy0 { >> status = "okay"; >> }; >> >> +&usb_2 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&usb2_en_state>; >> + >> + status = "okay"; >> +}; >> + >> +&usb_2_dwc3 { >> + dr_mode = "host"; >> + phy-names = "usb2-port0", "usb3-port0"; >> + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>; >> +}; >> + >> &xo_board_clk { >> clock-frequency = <38400000>; >> }; >> @@ -401,4 +414,13 @@ wake-pins { >> bias-pull-up; >> }; >> }; >> + >> + usb2_en_state: usb2-en-state { >> + /* TS3USB221A USB2.0 mux select */ >> + pins = "gpio24"; >> + function = "gpio"; >> + drive-strength = <2>; >> + bias-disable; >> + output-low; >> + }; >> };
nit I just noticed: s/sa8540-ride/sa8540p-ride/ please during the next spin! On Thu, May 04, 2023 at 11:33:44PM +0530, Krishna Kurapati PSSNV wrote: > > > On 5/2/2023 4:37 PM, Konrad Dybcio wrote: > > > > > > On 1.05.2023 16:34, Krishna Kurapati wrote: > > > There is now support for the multiport USB controller this uses so > > > enable it. > > > > > > The board only has a single port hooked up (despite it being wired up to > > > the multiport IP on the SoC). There's also a USB 2.0 mux hooked up, > > > which by default on boot is selected to mux properly. Grab the gpio > > > controlling that and ensure it stays in the right position so USB 2.0 > > > continues to be routed from the external port to the SoC. > > > > > > Signed-off-by: Andrew Halaney <ahalaney@redhat.com> > > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > > > --- > > same comments as patch 8 > > > > Konrad > > Hi Konrad, > > Sure, will add a default value for drive-strength for this pinctrl node. > > Hi Andrew Halaney, > > I currently don't have a Ride device with me to test this change. Can you > help test this patch on SA8540-Ride including (drive-strength = <2>;) > property (which I believe is the default value). > > I can test the same on SA8295-ADP and can push the next version quickly. > The patch here for sa8540p-ride already includes the drive strength. I did pull this on top of usb-next and it is working well for me in a quick sanity test. Konrad's pinctrl-names/pinctrl-0 swap is purely cosmetic of course, but for what is worth that works fine too. I'd add my Tested-by for this patch, but it seems silly since I authored the original :) Also, make CHECK_DTBS=y qcom/sa8540p-ride.dtb is still reporting issues, but other reviewers have highlighted that I believe. Just for the record though, make sure you get those silenced! I look forward to the next revision. Thanks, Andrew > Regards, > Krishna, > > > > arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++++++++++++++++++++++ > > > 1 file changed, 22 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts > > > index 24fa449d48a6..53d47593306e 100644 > > > --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts > > > +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts > > > @@ -309,6 +309,19 @@ &usb_2_qmpphy0 { > > > status = "okay"; > > > }; > > > +&usb_2 { > > > + pinctrl-names = "default"; > > > + pinctrl-0 = <&usb2_en_state>; > > > + > > > + status = "okay"; > > > +}; > > > + > > > +&usb_2_dwc3 { > > > + dr_mode = "host"; > > > + phy-names = "usb2-port0", "usb3-port0"; > > > + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>; > > > +}; > > > + > > > &xo_board_clk { > > > clock-frequency = <38400000>; > > > }; > > > @@ -401,4 +414,13 @@ wake-pins { > > > bias-pull-up; > > > }; > > > }; > > > + > > > + usb2_en_state: usb2-en-state { > > > + /* TS3USB221A USB2.0 mux select */ > > > + pins = "gpio24"; > > > + function = "gpio"; > > > + drive-strength = <2>; > > > + bias-disable; > > > + output-low; > > > + }; > > > }; >
diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 24fa449d48a6..53d47593306e 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -309,6 +309,19 @@ &usb_2_qmpphy0 { status = "okay"; }; +&usb_2 { + pinctrl-names = "default"; + pinctrl-0 = <&usb2_en_state>; + + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; + phy-names = "usb2-port0", "usb3-port0"; + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>; +}; + &xo_board_clk { clock-frequency = <38400000>; }; @@ -401,4 +414,13 @@ wake-pins { bias-pull-up; }; }; + + usb2_en_state: usb2-en-state { + /* TS3USB221A USB2.0 mux select */ + pins = "gpio24"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; };