diff mbox series

[v2] RISC-V: ICE for vlmul_ext_v intrinsic API

Message ID	20230426130602.3335312-1-yanzhang.wang@intel.com
State	Accepted
Headers	Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 68A7F3858C53 To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH v2] RISC-V: ICE for vlmul_ext_v intrinsic API Date: Wed, 26 Apr 2023 21:06:02 +0800 Message-Id: <20230426130602.3335312-1-yanzhang.wang@intel.com> In-Reply-To: <20230426120503.3207041-1-yanzhang.wang@intel.com> References: <20230426120503.3207041-1-yanzhang.wang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list From: "yanzhang.wang--- via Gcc-patches" <gcc-patches@gcc.gnu.org> Reply-To: yanzhang.wang@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org> X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?=
Series	[v2] RISC-V: ICE for vlmul_ext_v intrinsic API \| [v2] RISC-V: ICE for vlmul_ext_v intrinsic API

Checks

Context	Check	Description
snail/gcc-patch-check	success	Github commit url

Commit Message

Li, Pan2 via Gcc-patches April 26, 2023, 1:06 p.m. UTC

  From: Yanzhang Wang <yanzhang.wang@intel.com>

	PR 109617

gcc/ChangeLog:

	* config/riscv/vector-iterators.md: Support VNx2HI and VNX4DI when MIN_VLEN >= 128.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test.

Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Pan Li <pan2.li@intel.com>
---
 gcc/config/riscv/vector-iterators.md               |  3 ++-
 .../gcc.target/riscv/rvv/base/vlmul_ext-1.c        | 14 ++++++++++++++
 2 files changed, 16 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c

Comments

Li, Pan2 via Gcc-patches April 28, 2023, 10:36 a.m. UTC | #1

Kindly ping for this ICE fix.

Pan

-----Original Message-----
From: Wang, Yanzhang <yanzhang.wang@intel.com> 
Sent: Wednesday, April 26, 2023 9:06 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: [PATCH v2] RISC-V: ICE for vlmul_ext_v intrinsic API

From: Yanzhang Wang <yanzhang.wang@intel.com>

	PR 109617

gcc/ChangeLog:

	* config/riscv/vector-iterators.md: Support VNx2HI and VNX4DI when MIN_VLEN >= 128.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test.

Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Pan Li <pan2.li@intel.com>
---
 gcc/config/riscv/vector-iterators.md               |  3 ++-
 .../gcc.target/riscv/rvv/base/vlmul_ext-1.c        | 14 ++++++++++++++
 2 files changed, 16 insertions(+), 1 deletion(-)  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c

diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index a8e856161d3..033659930d1 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -189,6 +189,7 @@
   (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI (VNx16HI "TARGET_MIN_VLEN >= 128")
   (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI (VNx8SI "TARGET_MIN_VLEN >= 128")
   (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
+  (VNx4DI "TARGET_VECTOR_ELEN_64")
   (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
   (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
   (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
@@ -220,7 +221,7 @@
 
 (define_mode_iterator VLMULEXT32 [
   (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN >= 128")
-  (VNx1HI "TARGET_MIN_VLEN < 128")
+  (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN >= 128")
 ])
 
 (define_mode_iterator VLMULEXT64 [
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
new file mode 100644
index 00000000000..501d98c5897
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
+-fno-schedule-insns2" } */
+
+#include <riscv_vector.h>
+
+vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) {
+  return __riscv_vlmul_ext_v_i16mf4_i16m8(op1);
+}
+
+vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1) {
+  return __riscv_vlmul_ext_v_i64m2_i64m8(op1);
+}
+
+/* { dg-final { scan-assembler-times {vs8r.v\s+[,\sa-x0-9()]+} 2} } */
--
2.39.2

Kito Cheng May 2, 2023, 3:35 p.m. UTC | #2

committed, thanks for the patch :)

On Fri, Apr 28, 2023 at 6:37 PM Li, Pan2 via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Kindly ping for this ICE fix.
>
> Pan
>
> -----Original Message-----
> From: Wang, Yanzhang <yanzhang.wang@intel.com>
> Sent: Wednesday, April 26, 2023 9:06 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> Subject: [PATCH v2] RISC-V: ICE for vlmul_ext_v intrinsic API
>
> From: Yanzhang Wang <yanzhang.wang@intel.com>
>
>         PR 109617
>
> gcc/ChangeLog:
>
>         * config/riscv/vector-iterators.md: Support VNx2HI and VNX4DI when MIN_VLEN >= 128.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test.
>
> Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
> Co-authored-by: Pan Li <pan2.li@intel.com>
> ---
>  gcc/config/riscv/vector-iterators.md               |  3 ++-
>  .../gcc.target/riscv/rvv/base/vlmul_ext-1.c        | 14 ++++++++++++++
>  2 files changed, 16 insertions(+), 1 deletion(-)  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
>
> diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
> index a8e856161d3..033659930d1 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -189,6 +189,7 @@
>    (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI (VNx16HI "TARGET_MIN_VLEN >= 128")
>    (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI (VNx8SI "TARGET_MIN_VLEN >= 128")
>    (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
> +  (VNx4DI "TARGET_VECTOR_ELEN_64")
>    (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
>    (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
>    (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
> @@ -220,7 +221,7 @@
>
>  (define_mode_iterator VLMULEXT32 [
>    (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN >= 128")
> -  (VNx1HI "TARGET_MIN_VLEN < 128")
> +  (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN >= 128")
>  ])
>
>  (define_mode_iterator VLMULEXT64 [
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
> new file mode 100644
> index 00000000000..501d98c5897
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
> +-fno-schedule-insns2" } */
> +
> +#include <riscv_vector.h>
> +
> +vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) {
> +  return __riscv_vlmul_ext_v_i16mf4_i16m8(op1);
> +}
> +
> +vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1) {
> +  return __riscv_vlmul_ext_v_i64m2_i64m8(op1);
> +}
> +
> +/* { dg-final { scan-assembler-times {vs8r.v\s+[,\sa-x0-9()]+} 2} } */
> --
> 2.39.2
>

diff mbox series

Patch

diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index a8e856161d3..033659930d1 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -189,6 +189,7 @@ 
   (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI (VNx16HI "TARGET_MIN_VLEN >= 128")
   (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI (VNx8SI "TARGET_MIN_VLEN >= 128")
   (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
+  (VNx4DI "TARGET_VECTOR_ELEN_64")
   (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
   (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
   (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
@@ -220,7 +221,7 @@ 
 
 (define_mode_iterator VLMULEXT32 [
   (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN >= 128")
-  (VNx1HI "TARGET_MIN_VLEN < 128")
+  (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN >= 128")
 ])
 
 (define_mode_iterator VLMULEXT64 [
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
new file mode 100644
index 00000000000..501d98c5897
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include <riscv_vector.h>
+
+vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) {
+  return __riscv_vlmul_ext_v_i16mf4_i16m8(op1);
+}
+
+vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1) {
+  return __riscv_vlmul_ext_v_i64m2_i64m8(op1);
+}
+
+/* { dg-final { scan-assembler-times {vs8r.v\s+[,\sa-x0-9()]+} 2} } */