diff mbox series

[V2] perf cs-etm: Add fix for coresight trace for any range of CPUs

Message ID 20230421055253.83912-1-gankulkarni@os.amperecomputing.com
State New
Headers
Series [V2] perf cs-etm: Add fix for coresight trace for any range of CPUs |

Commit Message

Ganapatrao Kulkarni April 21, 2023, 5:52 a.m. UTC 
  The current implementation supports coresight trace decode for a range
of CPUs, if the first CPU is CPU0.

Perf report segfaults, if tried for sparse CPUs list and also for
any range of CPUs(non zero first CPU).

Adding a fix to perf report for any range of CPUs and for sparse list.

Signed-off-by: Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>
---

V2:
	Updated with review comments.
	Fixed for sparse list of CPUs also.

V1:
	[1] https://lore.kernel.org/lkml/20230419172101.78638-1-gankulkarni@os.amperecomputing.com/

 tools/perf/util/cs-etm.c | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

Comments

Arnaldo Carvalho de Melo April 29, 2023, 1:57 a.m. UTC | #1 
Em Thu, Apr 20, 2023 at 10:52:53PM -0700, Ganapatrao Kulkarni escreveu:
> The current implementation supports coresight trace decode for a range
> of CPUs, if the first CPU is CPU0.
> 
> Perf report segfaults, if tried for sparse CPUs list and also for
> any range of CPUs(non zero first CPU).
> 
> Adding a fix to perf report for any range of CPUs and for sparse list.

Can some ARM people please review this?

- Arnaldo
 
> Signed-off-by: Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>
> ---
> 
> V2:
> 	Updated with review comments.
> 	Fixed for sparse list of CPUs also.
> 
> V1:
> 	[1] https://lore.kernel.org/lkml/20230419172101.78638-1-gankulkarni@os.amperecomputing.com/
> 
>  tools/perf/util/cs-etm.c | 24 +++++++++++++++++++++++-
>  1 file changed, 23 insertions(+), 1 deletion(-)
> 
> diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c
> index 8dd81ddd9e4e..2003717f5779 100644
> --- a/tools/perf/util/cs-etm.c
> +++ b/tools/perf/util/cs-etm.c
> @@ -275,6 +275,25 @@ static int cs_etm__metadata_set_trace_id(u8 trace_chan_id, u64 *cpu_metadata)
>  		(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
>  	})
>  
> +/*
> + * Get a metadata for a specific cpu from an array.
> + *
> + */
> +static u64 *get_cpu_data(struct cs_etm_auxtrace *etm, int cpu)
> +{
> +	int i;
> +	u64 *metadata = NULL;
> +
> +	for (i = 0; i < etm->num_cpu; i++) {
> +		if (etm->metadata[i][CS_ETM_CPU] == (u64)cpu) {
> +			metadata = etm->metadata[i];
> +			break;
> +		}
> +	}
> +
> +	return metadata;
> +}
> +
>  /*
>   * Handle the PERF_RECORD_AUX_OUTPUT_HW_ID event.
>   *
> @@ -344,8 +363,11 @@ static int cs_etm__process_aux_output_hw_id(struct perf_session *session,
>  		return 0;
>  	}
>  
> +	cpu_data = get_cpu_data(etm, cpu);
> +	if (cpu_data == NULL)
> +		return err;
> +
>  	/* not one we've seen before - lets map it */
> -	cpu_data = etm->metadata[cpu];
>  	err = cs_etm__map_trace_id(trace_chan_id, cpu_data);
>  	if (err)
>  		return err;
> -- 
> 2.39.2
>
Suzuki K Poulose May 3, 2023, 1:31 p.m. UTC | #2 
On 29/04/2023 02:57, Arnaldo Carvalho de Melo wrote:
> Em Thu, Apr 20, 2023 at 10:52:53PM -0700, Ganapatrao Kulkarni escreveu:
>> The current implementation supports coresight trace decode for a range
>> of CPUs, if the first CPU is CPU0.
>>
>> Perf report segfaults, if tried for sparse CPUs list and also for
>> any range of CPUs(non zero first CPU).
>>
>> Adding a fix to perf report for any range of CPUs and for sparse list.
> 
> Can some ARM people please review this?
> 
> - Arnaldo

Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>

Suzuki
diff mbox series

Patch

diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c
index 8dd81ddd9e4e..2003717f5779 100644
--- a/tools/perf/util/cs-etm.c
+++ b/tools/perf/util/cs-etm.c
@@ -275,6 +275,25 @@  static int cs_etm__metadata_set_trace_id(u8 trace_chan_id, u64 *cpu_metadata)
 		(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
 	})
 
+/*
+ * Get a metadata for a specific cpu from an array.
+ *
+ */
+static u64 *get_cpu_data(struct cs_etm_auxtrace *etm, int cpu)
+{
+	int i;
+	u64 *metadata = NULL;
+
+	for (i = 0; i < etm->num_cpu; i++) {
+		if (etm->metadata[i][CS_ETM_CPU] == (u64)cpu) {
+			metadata = etm->metadata[i];
+			break;
+		}
+	}
+
+	return metadata;
+}
+
 /*
  * Handle the PERF_RECORD_AUX_OUTPUT_HW_ID event.
  *
@@ -344,8 +363,11 @@  static int cs_etm__process_aux_output_hw_id(struct perf_session *session,
 		return 0;
 	}
 
+	cpu_data = get_cpu_data(etm, cpu);
+	if (cpu_data == NULL)
+		return err;
+
 	/* not one we've seen before - lets map it */
-	cpu_data = etm->metadata[cpu];
 	err = cs_etm__map_trace_id(trace_chan_id, cpu_data);
 	if (err)
 		return err;