[v5,03/10] RISC-V:autovec: Add auto-vectorization support functions
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Commit Message
2023-04-24 Michael Collison <collison@rivosinc.com>
Juzhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-v.cc
(riscv_vector_preferred_simd_mode): New function.
(get_mask_policy_no_pred): Ditto.
(get_tail_policy_no_pred): Ditto.
(riscv_vector_mask_mode_p): Ditto.
(riscv_vector_get_mask_mode): Ditto.
---
gcc/config/riscv/riscv-v.cc | 79 +++++++++++++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
Comments
On 4/26/23 15:45, Michael Collison wrote:
> 2023-04-24 Michael Collison <collison@rivosinc.com>
> Juzhe Zhong <juzhe.zhong@rivai.ai>
>
> * config/riscv/riscv-v.cc
> (riscv_vector_preferred_simd_mode): New function.
> (get_mask_policy_no_pred): Ditto.
> (get_tail_policy_no_pred): Ditto.
> (riscv_vector_mask_mode_p): Ditto.
> (riscv_vector_get_mask_mode): Ditto.
> ---
> @@ -176,6 +178,46 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul)
> return ratio;
> }
>
> +/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE for RVV. */
Doesn't really tell me much.
/* Return the preferred SIMD mode for MODE. */
> @@ -421,6 +463,43 @@ get_avl_type_rtx (enum avl_type type)
> return gen_int_mode (type, Pmode);
> }
>
> +rtx
> +get_mask_policy_no_pred ()
> +{
> + return get_mask_policy_for_pred (PRED_TYPE_none);
> +}
> +
> +rtx
> +get_tail_policy_no_pred ()
> +{
> + return get_mask_policy_for_pred (PRED_TYPE_none);
> +}
I'm guessing the call in get_tail_policy_no_pred should have been to
get_tail_policy_for_pred rather than get_mask_policy_for_pred.
^^^^ ^^^^
A short function comment for the two functions seems appropriate.
> +
> +/* Implement TARGET_VECTORIZE_GET_MASK_MODE for RVV. */
How about
/* Return the appropriate mask mode for MODE. */
OK with the trivial fixes noted above.
Jeff
> @@ -176,6 +178,46 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul)
> return ratio;
> }
>
> +/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE for RVV. */
> +
> +machine_mode
> +riscv_vector_preferred_simd_mode (scalar_mode mode)
JuZhe's patch[1] has been implemented and his version handles
types/modes in the right way IMO,
so I would like to take his version for this hook.
[1] https://patchwork.sourceware.org/project/gcc/patch/20230419164214.1032017-3-juzhe.zhong@rivai.ai/
HI Kito,
I see there have been many comments on the
"riscv_vector_preferred_simd_mode" hook, is there an updated version?
On 5/3/23 06:53, Kito Cheng wrote:
>> @@ -176,6 +178,46 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul)
>> return ratio;
>> }
>>
>> +/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE for RVV. */
>> +
>> +machine_mode
>> +riscv_vector_preferred_simd_mode (scalar_mode mode)
> JuZhe's patch[1] has been implemented and his version handles
> types/modes in the right way IMO,
> so I would like to take his version for this hook.
>
> [1] https://patchwork.sourceware.org/project/gcc/patch/20230419164214.1032017-3-juzhe.zhong@rivai.ai/
On 5/3/23 11:31, Michael Collison wrote:
> HI Kito,
>
> I see there have been many comments on the
> "riscv_vector_preferred_simd_mode" hook, is there an updated version?
I think there's a version on the trunk now. So if there's updates to
do, let's do them relative to what's on the trunk.
Jeff
@@ -39,9 +39,11 @@
#include "emit-rtl.h"
#include "tm_p.h"
#include "target.h"
+#include "targhooks.h"
#include "expr.h"
#include "optabs.h"
#include "tm-constrs.h"
+#include "riscv-vector-builtins.h"
#include "rtx-vector-builder.h"
using namespace riscv_vector;
@@ -176,6 +178,46 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul)
return ratio;
}
+/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE for RVV. */
+
+machine_mode
+riscv_vector_preferred_simd_mode (scalar_mode mode)
+{
+ if (!TARGET_VECTOR)
+ return word_mode;
+
+ switch (mode)
+ {
+ case E_QImode:
+ return VNx8QImode;
+ break;
+ case E_HImode:
+ return VNx4HImode;
+ break;
+ case E_SImode:
+ return VNx2SImode;
+ break;
+ case E_DImode:
+ if (riscv_vector_elen_flags != MASK_VECTOR_ELEN_32
+ && riscv_vector_elen_flags != MASK_VECTOR_ELEN_FP_32)
+ return VNx1DImode;
+ break;
+ case E_SFmode:
+ if (TARGET_HARD_FLOAT && riscv_vector_elen_flags != MASK_VECTOR_ELEN_32
+ && riscv_vector_elen_flags != MASK_VECTOR_ELEN_64)
+ return VNx2SFmode;
+ break;
+ case E_DFmode:
+ if (TARGET_DOUBLE_FLOAT && TARGET_VECTOR_ELEN_FP_64)
+ return VNx1DFmode;
+ break;
+ default:
+ break;
+ }
+
+ return word_mode;
+}
+
/* Emit an RVV unmask && vl mov from SRC to DEST. */
static void
emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len,
@@ -421,6 +463,43 @@ get_avl_type_rtx (enum avl_type type)
return gen_int_mode (type, Pmode);
}
+rtx
+get_mask_policy_no_pred ()
+{
+ return get_mask_policy_for_pred (PRED_TYPE_none);
+}
+
+rtx
+get_tail_policy_no_pred ()
+{
+ return get_mask_policy_for_pred (PRED_TYPE_none);
+}
+
+/* Return true if it is a RVV mask mode. */
+bool
+riscv_vector_mask_mode_p (machine_mode mode)
+{
+ return (mode == VNx1BImode || mode == VNx2BImode || mode == VNx4BImode
+ || mode == VNx8BImode || mode == VNx16BImode || mode == VNx32BImode
+ || mode == VNx64BImode);
+}
+
+/* Implement TARGET_VECTORIZE_GET_MASK_MODE for RVV. */
+
+opt_machine_mode
+riscv_vector_get_mask_mode (machine_mode mode)
+{
+ machine_mode mask_mode;
+ int nf = 1;
+
+ FOR_EACH_MODE_IN_CLASS (mask_mode, MODE_VECTOR_BOOL)
+ if (GET_MODE_INNER (mask_mode) == BImode
+ && known_eq (GET_MODE_NUNITS (mask_mode) * nf, GET_MODE_NUNITS (mode))
+ && riscv_vector_mask_mode_p (mask_mode))
+ return mask_mode;
+ return default_get_mask_mode (mode);
+}
+
/* Return the RVV vector mode that has NUNITS elements of mode INNER_MODE.
This function is not only used by builtins, but also will be used by
auto-vectorization in the future. */