diff mbox series

[v5,05/11] RISC-V: Add AMO release bits

Message ID 20230427162301.1151333-6-patrick@rivosinc.com
State Accepted
Headers
Series RISC-V: Implement ISA Manual Table A.6 Mappings |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Patrick O'Neill April 27, 2023, 4:22 p.m. UTC 
  This patch sets the relevant .rl bits on amo operations.

2023-04-27 Patrick O'Neill <patrick@rivosinc.com>

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_print_operand): change behavior
	of %A to include release bits.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
 gcc/config/riscv/riscv.cc | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

Comments

Jeff Law April 28, 2023, 5:34 p.m. UTC | #1 
On 4/27/23 10:22, Patrick O'Neill wrote:
> This patch sets the relevant .rl bits on amo operations.
> 
> 2023-04-27 Patrick O'Neill <patrick@rivosinc.com>
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/riscv.cc (riscv_print_operand): change behavior
> 	of %A to include release bits.
Capitalize "change" in the ChangeLog entry.  OK with that nit fixed.

jeff
Patrick O'Neill May 2, 2023, 8:16 p.m. UTC | #2 
On 4/28/23 10:34, Jeff Law wrote:
>
>
> On 4/27/23 10:22, Patrick O'Neill wrote:
>> This patch sets the relevant .rl bits on amo operations.
>>
>> 2023-04-27 Patrick O'Neill <patrick@rivosinc.com>
>>
>> gcc/ChangeLog:
>>
>>     * config/riscv/riscv.cc (riscv_print_operand): change behavior
>>     of %A to include release bits.
> Capitalize "change" in the ChangeLog entry.  OK with that nit fixed.
>
> jeff

Capitalized "change" and committed.

gcc/ChangeLog:

     * config/riscv/riscv.cc (riscv_print_operand): Change behavior
     of %A to include release bits.

Patrick
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 02eb5125ac1..d46781d8981 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4503,8 +4503,13 @@  riscv_print_operand (FILE *file, rtx op, int letter)
       break;
 
     case 'A':
-      if (riscv_memmodel_needs_amo_acquire (model))
+      if (riscv_memmodel_needs_amo_acquire (model)
+	  && riscv_memmodel_needs_release_fence (model))
+	fputs (".aqrl", file);
+      else if (riscv_memmodel_needs_amo_acquire (model))
 	fputs (".aq", file);
+      else if (riscv_memmodel_needs_release_fence (model))
+	fputs (".rl", file);
       break;
 
     case 'F':