ARM: dts: broadcom: add missing cache properties
Commit Message
As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:
bcm963148.dtb: l2-cache0: 'cache-unified' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
arch/arm/boot/dts/bcm47622.dtsi | 1 +
arch/arm/boot/dts/bcm63148.dtsi | 1 +
arch/arm/boot/dts/bcm63178.dtsi | 1 +
arch/arm/boot/dts/bcm6756.dtsi | 1 +
arch/arm/boot/dts/bcm6846.dtsi | 1 +
arch/arm/boot/dts/bcm6855.dtsi | 1 +
arch/arm/boot/dts/bcm6878.dtsi | 1 +
7 files changed, 7 insertions(+)
Comments
On 04/23/2023 08:09 AM, Krzysztof Kozlowski wrote:
> As all level 2 and level 3 caches are unified, add required
> cache-unified properties to fix warnings like:
>
> bcm963148.dtb: l2-cache0: 'cache-unified' is a required property
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> arch/arm/boot/dts/bcm47622.dtsi | 1 +
> arch/arm/boot/dts/bcm63148.dtsi | 1 +
> arch/arm/boot/dts/bcm63178.dtsi | 1 +
> arch/arm/boot/dts/bcm6756.dtsi | 1 +
> arch/arm/boot/dts/bcm6846.dtsi | 1 +
> arch/arm/boot/dts/bcm6855.dtsi | 1 +
> arch/arm/boot/dts/bcm6878.dtsi | 1 +
> 7 files changed, 7 insertions(+)
>
Reviewed-by: William Zhang <william.zhang@broadcom.com>
On Sun, 23 Apr 2023 17:09:43 +0200, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
> As all level 2 and level 3 caches are unified, add required
> cache-unified properties to fix warnings like:
>
> bcm963148.dtb: l2-cache0: 'cache-unified' is a required property
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks!
--
Florian
@@ -52,6 +52,7 @@ CA7_3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
};
};
@@ -36,6 +36,7 @@ B15_1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
};
};
@@ -44,6 +44,7 @@ CA7_2: cpu@2 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
};
};
@@ -52,6 +52,7 @@ CA7_3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
};
};
@@ -36,6 +36,7 @@ CA7_1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
};
};
@@ -44,6 +44,7 @@ CA7_2: cpu@2 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
};
};
@@ -36,6 +36,7 @@ CA7_1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
};
};