diff mbox series

[V2] RISC-V: Eliminate redundant vsetvli for duplicate AVL def

Message ID 20230423121859.95799-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series [V2] RISC-V: Eliminate redundant vsetvli for duplicate AVL def |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai April 23, 2023, 12:18 p.m. UTC 
  From: Juzhe-Zhong <juzhe.zhong@rivai.ai>

This patch is the V2 patch:https://patchwork.sourceware.org/project/gcc/patch/20230328010124.235703-1-juzhe.zhong@rivai.ai/

Address comments from Jeff. Add comments for all_avail_in_compatible_p and refine comments of codes.
 
gcc/ChangeLog:

        * config/riscv/riscv-vsetvl.cc (vector_infos_manager::all_avail_in_compatible_p): New function.
        (pass_vsetvl::refine_vsetvls): Optimize vsetvls.
        * config/riscv/riscv-vsetvl.h: New function.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/vsetvl/avl_single-102.c: New test.

---
 gcc/config/riscv/riscv-vsetvl.cc              | 44 +++++++++++++++++--
 gcc/config/riscv/riscv-vsetvl.h               |  1 +
 .../riscv/rvv/vsetvl/avl_single-102.c         | 16 +++++++
 3 files changed, 58 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c

Comments

Kito Cheng April 24, 2023, 6:27 a.m. UTC | #1 
Committed, thanks :)

On Sun, Apr 23, 2023 at 8:19 PM <juzhe.zhong@rivai.ai> wrote:
>
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> This patch is the V2 patch:https://patchwork.sourceware.org/project/gcc/patch/20230328010124.235703-1-juzhe.zhong@rivai.ai/
>
> Address comments from Jeff. Add comments for all_avail_in_compatible_p and refine comments of codes.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-vsetvl.cc (vector_infos_manager::all_avail_in_compatible_p): New function.
>         (pass_vsetvl::refine_vsetvls): Optimize vsetvls.
>         * config/riscv/riscv-vsetvl.h: New function.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/vsetvl/avl_single-102.c: New test.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc              | 44 +++++++++++++++++--
>  gcc/config/riscv/riscv-vsetvl.h               |  1 +
>  .../riscv/rvv/vsetvl/avl_single-102.c         | 16 +++++++
>  3 files changed, 58 insertions(+), 3 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
> index fa68b8a0462..89a45a428a4 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -2446,6 +2446,26 @@ vector_infos_manager::all_same_ratio_p (sbitmap bitdata) const
>    return true;
>  }
>
> +/* Return TRUE if the incoming vector configuration state
> +   to CFG_BB is compatible with the vector configuration
> +   state in CFG_BB, FALSE otherwise.  */
> +bool
> +vector_infos_manager::all_avail_in_compatible_p (const basic_block cfg_bb) const
> +{
> +  const auto &info = vector_block_infos[cfg_bb->index].local_dem;
> +  sbitmap avin = vector_avin[cfg_bb->index];
> +  unsigned int bb_index;
> +  sbitmap_iterator sbi;
> +  EXECUTE_IF_SET_IN_BITMAP (avin, 0, bb_index, sbi)
> +  {
> +    const auto &avin_info
> +      = static_cast<const vl_vtype_info &> (*vector_exprs[bb_index]);
> +    if (!info.compatible_p (avin_info))
> +      return false;
> +  }
> +  return true;
> +}
> +
>  bool
>  vector_infos_manager::all_same_avl_p (const basic_block cfg_bb,
>                                       sbitmap bitdata) const
> @@ -3816,9 +3836,27 @@ pass_vsetvl::refine_vsetvls (void) const
>           m_vector_manager->to_refine_vsetvls.add (rinsn);
>           continue;
>         }
> -      rinsn = PREV_INSN (rinsn);
> -      rtx new_pat = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, info, NULL_RTX);
> -      change_insn (rinsn, new_pat);
> +
> +      /* If all incoming edges to a block have a vector state that is compatbile
> +        with the block. In such a case we need not emit a vsetvl in the current
> +        block.  */
> +
> +      gcc_assert (has_vtype_op (insn->rtl ()));
> +      rinsn = PREV_INSN (insn->rtl ());
> +      gcc_assert (vector_config_insn_p (PREV_INSN (insn->rtl ())));
> +      if (m_vector_manager->all_avail_in_compatible_p (cfg_bb))
> +       {
> +         size_t id = m_vector_manager->get_expr_id (info);
> +         if (bitmap_bit_p (m_vector_manager->vector_del[cfg_bb->index], id))
> +           continue;
> +         eliminate_insn (rinsn);
> +       }
> +      else
> +       {
> +         rtx new_pat
> +           = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, info, NULL_RTX);
> +         change_insn (rinsn, new_pat);
> +       }
>      }
>  }
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.h b/gcc/config/riscv/riscv-vsetvl.h
> index 9041eee1281..d7a6c14e931 100644
> --- a/gcc/config/riscv/riscv-vsetvl.h
> +++ b/gcc/config/riscv/riscv-vsetvl.h
> @@ -452,6 +452,7 @@ public:
>    bool all_same_ratio_p (sbitmap) const;
>
>    bool all_empty_predecessor_p (const basic_block) const;
> +  bool all_avail_in_compatible_p (const basic_block) const;
>
>    void release (void);
>    void create_bitmap_vectors (void);
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c
> new file mode 100644
> index 00000000000..8236d4e7f18
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c
> @@ -0,0 +1,16 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
> +
> +#include "riscv_vector.h"
> +
> +void f (int8_t* base1,int8_t* base2,int8_t* out,int n)
> +{
> +  vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
> +  for (int i = 0; i < n; i++){
> +    v = __riscv_vor_vx_i8mf4 (v, 101, 32);
> +    v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
> +  }
> +  __riscv_vse8_v_i8mf4 (out, v, 32);
> +}
> +
> +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
> --
> 2.36.1
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index fa68b8a0462..89a45a428a4 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -2446,6 +2446,26 @@  vector_infos_manager::all_same_ratio_p (sbitmap bitdata) const
   return true;
 }
 
+/* Return TRUE if the incoming vector configuration state
+   to CFG_BB is compatible with the vector configuration
+   state in CFG_BB, FALSE otherwise.  */
+bool
+vector_infos_manager::all_avail_in_compatible_p (const basic_block cfg_bb) const
+{
+  const auto &info = vector_block_infos[cfg_bb->index].local_dem;
+  sbitmap avin = vector_avin[cfg_bb->index];
+  unsigned int bb_index;
+  sbitmap_iterator sbi;
+  EXECUTE_IF_SET_IN_BITMAP (avin, 0, bb_index, sbi)
+  {
+    const auto &avin_info
+      = static_cast<const vl_vtype_info &> (*vector_exprs[bb_index]);
+    if (!info.compatible_p (avin_info))
+      return false;
+  }
+  return true;
+}
+
 bool
 vector_infos_manager::all_same_avl_p (const basic_block cfg_bb,
 				      sbitmap bitdata) const
@@ -3816,9 +3836,27 @@  pass_vsetvl::refine_vsetvls (void) const
 	  m_vector_manager->to_refine_vsetvls.add (rinsn);
 	  continue;
 	}
-      rinsn = PREV_INSN (rinsn);
-      rtx new_pat = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, info, NULL_RTX);
-      change_insn (rinsn, new_pat);
+
+      /* If all incoming edges to a block have a vector state that is compatbile
+	 with the block. In such a case we need not emit a vsetvl in the current
+	 block.  */
+
+      gcc_assert (has_vtype_op (insn->rtl ()));
+      rinsn = PREV_INSN (insn->rtl ());
+      gcc_assert (vector_config_insn_p (PREV_INSN (insn->rtl ())));
+      if (m_vector_manager->all_avail_in_compatible_p (cfg_bb))
+	{
+	  size_t id = m_vector_manager->get_expr_id (info);
+	  if (bitmap_bit_p (m_vector_manager->vector_del[cfg_bb->index], id))
+	    continue;
+	  eliminate_insn (rinsn);
+	}
+      else
+	{
+	  rtx new_pat
+	    = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, info, NULL_RTX);
+	  change_insn (rinsn, new_pat);
+	}
     }
 }
 
diff --git a/gcc/config/riscv/riscv-vsetvl.h b/gcc/config/riscv/riscv-vsetvl.h
index 9041eee1281..d7a6c14e931 100644
--- a/gcc/config/riscv/riscv-vsetvl.h
+++ b/gcc/config/riscv/riscv-vsetvl.h
@@ -452,6 +452,7 @@  public:
   bool all_same_ratio_p (sbitmap) const;
 
   bool all_empty_predecessor_p (const basic_block) const;
+  bool all_avail_in_compatible_p (const basic_block) const;
 
   void release (void);
   void create_bitmap_vectors (void);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c
new file mode 100644
index 00000000000..8236d4e7f18
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c
@@ -0,0 +1,16 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t* base1,int8_t* base2,int8_t* out,int n)
+{
+  vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
+  for (int i = 0; i < n; i++){
+    v = __riscv_vor_vx_i8mf4 (v, 101, 32);
+    v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
+  }
+  __riscv_vse8_v_i8mf4 (out, v, 32);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */