diff mbox series

arm64: dts: ti: k3-j721s2-main: fix msmc node

Message ID 20230412173609.1307837-1-u-kumar1@ti.com
State New
Headers
Series arm64: dts: ti: k3-j721s2-main: fix msmc node |

Commit Message

Kumar, Udit April 12, 2023, 5:36 p.m. UTC 
  On J721S2 SOC, l3cache-sram size is configured as zero by
system firmware.
Also top 64K of msmc_ram (0x703F_0000 to 0x703F_FFFF) is used by system
firmware tifs-sram.

This patch removes l3cache-sram node and update range for tifs-sram.

Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC")

Signed-off-by: Udit Kumar <u-kumar1@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

Comments

Nishanth Menon April 12, 2023, 7:56 p.m. UTC | #1 
On 23:06-20230412, Udit Kumar wrote:
> On J721S2 SOC, l3cache-sram size is configured as zero by
> system firmware.
> Also top 64K of msmc_ram (0x703F_0000 to 0x703F_FFFF) is used by system
> firmware tifs-sram.
> 
> This patch removes l3cache-sram node and update range for tifs-sram.
> 
> Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC")
> 
> Signed-off-by: Udit Kumar <u-kumar1@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 7 ++-----
>  1 file changed, 2 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index 2dd7865f7654..cbc784f915a9 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -17,13 +17,10 @@ atf-sram@0 {
>  			reg = <0x0 0x20000>;
>  		};
>  
> -		tifs-sram@1f0000 {
> -			reg = <0x1f0000 0x10000>;
> +		tifs-sram@3f0000 {
> +			reg = <0x3f0000 0x10000>;
>  		};
>  
> -		l3cache-sram@200000 {
> -			reg = <0x200000 0x200000>;
> -		};
>  	};
>  
>  	gic500: interrupt-controller@1800000 {
> -- 
> 2.34.1
> 

Are you saying that j721s2 is incapable of l3 cache? say some level 1
errata?

or is it because, the chip is really capable of l3 cache and we are
really setting it to 0?

https://git.ti.com/cgit/k3-image-gen/k3-image-gen/tree/soc/j721s2/evm/board-cfg.c#n71

unless the chip has an errata, you are supposed to fix it up based on
configuration by using the API and this patch is a NAK
https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/general/core.html#tisci-query-msmc
Kumar, Udit April 13, 2023, 5:15 a.m. UTC | #2 
Hi Nishanth,

On 13/04/23 01:26, Nishanth Menon wrote:
> On 23:06-20230412, Udit Kumar wrote:
>> On J721S2 SOC, l3cache-sram size is configured as zero by
>> system firmware.
>> Also top 64K of msmc_ram (0x703F_0000 to 0x703F_FFFF) is used by system
>> firmware tifs-sram.
>>
>> This patch removes l3cache-sram node and update range for tifs-sram.
>>
>> Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC")
>>
>> Signed-off-by: Udit Kumar <u-kumar1@ti.com>
>> ---
>>   arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 7 ++-----
>>   1 file changed, 2 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>> index 2dd7865f7654..cbc784f915a9 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>> @@ -17,13 +17,10 @@ atf-sram@0 {
>>   			reg = <0x0 0x20000>;
>>   		};
>>   
>> -		tifs-sram@1f0000 {
>> -			reg = <0x1f0000 0x10000>;
>> +		tifs-sram@3f0000 {
>> +			reg = <0x3f0000 0x10000>;
>>   		};
>>   
>> -		l3cache-sram@200000 {
>> -			reg = <0x200000 0x200000>;
>> -		};
>>   	};
>>   
>>   	gic500: interrupt-controller@1800000 {
>> -- 
>> 2.34.1
>>
> Are you saying that j721s2 is incapable of l3 cache? say some level 1
> errata?
No
> or is it because, the chip is really capable of l3 cache and we are
> really setting it to 0?
>
> https://git.ti.com/cgit/k3-image-gen/k3-image-gen/tree/soc/j721s2/evm/board-cfg.c#n71
This is because, l3 cache size is set to zero.
> unless the chip has an errata, you are supposed to fix it up based on
> configuration by using the API and this patch is a NAK
> https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/general/core.html#tisci-query-msmc
ok
Vignesh Raghavendra April 13, 2023, 5:23 a.m. UTC | #3 
Hi Udit,

On 13/04/23 10:45, Udit Kumar wrote:
> Hi Nishanth,
> 
> On 13/04/23 01:26, Nishanth Menon wrote:
>> On 23:06-20230412, Udit Kumar wrote:
>>> On J721S2 SOC, l3cache-sram size is configured as zero by
>>> system firmware.
>>> Also top 64K of msmc_ram (0x703F_0000 to 0x703F_FFFF) is used by system
>>> firmware tifs-sram.
>>>
>>> This patch removes l3cache-sram node and update range for tifs-sram.
>>>
>>> Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2
>>> SoC")
>>>
>>> Signed-off-by: Udit Kumar <u-kumar1@ti.com>
>>> ---
>>>   arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 7 ++-----
>>>   1 file changed, 2 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>>> b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>>> index 2dd7865f7654..cbc784f915a9 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>>> @@ -17,13 +17,10 @@ atf-sram@0 {
>>>               reg = <0x0 0x20000>;
>>>           };
>>>   -        tifs-sram@1f0000 {
>>> -            reg = <0x1f0000 0x10000>;
>>> +        tifs-sram@3f0000 {
>>> +            reg = <0x3f0000 0x10000>;
>>>           };
>>>   -        l3cache-sram@200000 {
>>> -            reg = <0x200000 0x200000>;
>>> -        };
>>>       };
>>>         gic500: interrupt-controller@1800000 {
>>> -- 
>>> 2.34.1
>>>
>> Are you saying that j721s2 is incapable of l3 cache? say some level 1
>> errata?
> No
>> or is it because, the chip is really capable of l3 cache and we are
>> really setting it to 0?
>>
>> https://git.ti.com/cgit/k3-image-gen/k3-image-gen/tree/soc/j721s2/evm/board-cfg.c#n71
> This is because, l3 cache size is set to zero.
>> unless the chip has an errata, you are supposed to fix it up based on
>> configuration by using the API and this patch is a NAK
>> https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/general/core.html#tisci-query-msmc
> ok

U-Boot already does this. See fdt_fixup_msmc_ram() at board/ti/j721s2/evm.c

tifs-sram fixup probably is still needed and possible bug in the original patch?
Kumar, Udit April 13, 2023, 5:57 a.m. UTC | #4 
Thanks Raghavendra

On 13/04/23 10:53, Vignesh Raghavendra wrote:
> Hi Udit,
>
> On 13/04/23 10:45, Udit Kumar wrote:
>> Hi Nishanth,
>>
>> On 13/04/23 01:26, Nishanth Menon wrote:
>>> On 23:06-20230412, Udit Kumar wrote:
>>>> [..]
>>> Are you saying that j721s2 is incapable of l3 cache? say some level 1
>>> errata?
>> No
>>> or is it because, the chip is really capable of l3 cache and we are
>>> really setting it to 0?
>>>
>>> https://git.ti.com/cgit/k3-image-gen/k3-image-gen/tree/soc/j721s2/evm/board-cfg.c#n71
>> This is because, l3 cache size is set to zero.
>>> unless the chip has an errata, you are supposed to fix it up based on
>>> configuration by using the API and this patch is a NAK
>>> https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/general/core.html#tisci-query-msmc
>> ok
> U-Boot already does this. See fdt_fixup_msmc_ram() at board/ti/j721s2/evm.c
>
> tifs-sram fixup probably is still needed and possible bug in the original patch?


Let me fix in u-boot


Regards

Udit

>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 2dd7865f7654..cbc784f915a9 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -17,13 +17,10 @@  atf-sram@0 {
 			reg = <0x0 0x20000>;
 		};
 
-		tifs-sram@1f0000 {
-			reg = <0x1f0000 0x10000>;
+		tifs-sram@3f0000 {
+			reg = <0x3f0000 0x10000>;
 		};
 
-		l3cache-sram@200000 {
-			reg = <0x200000 0x200000>;
-		};
 	};
 
 	gic500: interrupt-controller@1800000 {