diff mbox series

[v3,3/3] mmc: sdhci-of-arasan: Skip setting clock delay for 400KHz

Message ID 20230403102551.3763054-4-sai.krishna.potthuri@amd.com
State New
Headers
Series mmc: sdhci-of-arasan: Add eMMC5.1 support for Xilinx Versal Net |

Commit Message

Sai Krishna Potthuri April 3, 2023, 10:25 a.m. UTC 
  Clock delay settings are not defined for 400KHz, so add frequency check
to skip calling the clock delay settings when frequency is <=400KHz.

Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
---
 drivers/mmc/host/sdhci-of-arasan.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Adrian Hunter April 11, 2023, 10:14 a.m. UTC | #1 
On 3/04/23 13:25, Sai Krishna Potthuri wrote:
> Clock delay settings are not defined for 400KHz, so add frequency check
> to skip calling the clock delay settings when frequency is <=400KHz.
> 
> Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci-of-arasan.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
> index c3fecb8ba66e..d9a29c346745 100644
> --- a/drivers/mmc/host/sdhci-of-arasan.c
> +++ b/drivers/mmc/host/sdhci-of-arasan.c
> @@ -413,7 +413,7 @@ static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
>  	}
>  
>  	/* Set the Input and Output Clock Phase Delays */
> -	if (clk_data->set_clk_delays)
> +	if (clk_data->set_clk_delays && clock > PHY_CLK_TOO_SLOW_HZ)
>  		clk_data->set_clk_delays(host);
>  
>  	if (sdhci_arasan->internal_phy_reg && clock >= MIN_PHY_CLK_HZ) {
diff mbox series

Patch

diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index c3fecb8ba66e..d9a29c346745 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -413,7 +413,7 @@  static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
 	}
 
 	/* Set the Input and Output Clock Phase Delays */
-	if (clk_data->set_clk_delays)
+	if (clk_data->set_clk_delays && clock > PHY_CLK_TOO_SLOW_HZ)
 		clk_data->set_clk_delays(host);
 
 	if (sdhci_arasan->internal_phy_reg && clock >= MIN_PHY_CLK_HZ) {