[aarch64] Use op_mode instead of vmode for op0, op1 in aarch64_vectorize_vec_perm_const
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[8.43.85.97]) by mx.google.com with ESMTPS id d21-20020a17090694d500b00726e16c2d4fsi1385586ejy.178.2022.07.14.03.56.28 for <ouuuleilei@gmail.com> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 03:56:28 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=WqS5eqTG; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 50CC13887F5F for <ouuuleilei@gmail.com>; Thu, 14 Jul 2022 10:56:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 50CC13887F5F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1657796187; bh=1gmqMqZjsSv2fG0Ehl1M9KGPA2VIiJFIOF8RnuJrduU=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=WqS5eqTGp3YMIiSVmeZUPNbx7Hk8PSOdS6T+8nSxcFL7X3OgzrB+GycnB/252zqJf 8PAu6oA6OnsTGQzjuYfzxeiEO+zdQhPf9caPT99F7/VSuuwye7orbVhdzeZJBf66KW gFOCpgI45U6gNi8SJf70qgqLrHL5oSWBtUuq3fPg= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by sourceware.org (Postfix) with ESMTPS id 198F03856271 for <gcc-patches@gcc.gnu.org>; Thu, 14 Jul 2022 10:55:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 198F03856271 Received: by mail-ed1-x52a.google.com with SMTP id g1so1861551edb.12 for <gcc-patches@gcc.gnu.org>; Thu, 14 Jul 2022 03:55:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=1gmqMqZjsSv2fG0Ehl1M9KGPA2VIiJFIOF8RnuJrduU=; b=BQwNE/JjgHGtSJfwXyobCfVtbBh/9Qnmc+yzqdvs/pDRm2HNKGcNcXujaJu84U0Kgv il3Gbv+PTRiYIFmifbvlmy+KxaT4mlj+4SZhKTs0hYGE4Vnq8xqEkr0f3GYJ4BiKykXr XkkbbuSXYen9kWybOJBztFbl8rfvQYXqG9ieK+5KC+QYMVKsphpwFnlenlG3GoCeFDv/ lKVV91mRyZedGQefr6J3ImKl3I38xiFhL/b08LeClWE71OZN7Fv4DJYI9h03HEGdYp3I Xm0BKRiNXv3x9k+on7Yojm7ERmOxnl+KqawfdDqpLUl2PcJLubrZne28S/FJwnQG3x2r FmtQ== X-Gm-Message-State: AJIora8LMHZ0RwvaAplhZ8+dkzLj+ozxWfxxz+jy5j3+T7wdSD6oxoz6 53j9dXN5i17UZoLZPI85pMw6SyPAgK0Gc5tASVaLtaXSWvzYAsNK X-Received: by 2002:a05:6402:3443:b0:43a:f555:e9da with SMTP id l3-20020a056402344300b0043af555e9damr10031421edc.199.1657796141732; Thu, 14 Jul 2022 03:55:41 -0700 (PDT) MIME-Version: 1.0 Date: Thu, 14 Jul 2022 16:25:05 +0530 Message-ID: <CAAgBjM=9xQLW1DrVs2YSftpbWvF4umgdgYAAzVsXuxVDOBbN0Q@mail.gmail.com> Subject: [aarch64] Use op_mode instead of vmode for op0, op1 in aarch64_vectorize_vec_perm_const To: gcc Patches <gcc-patches@gcc.gnu.org>, Richard Sandiford <richard.sandiford@arm.com> Content-Type: multipart/mixed; boundary="00000000000023819305e3c1bec5" X-Spam-Status: No, score=-9.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> From: Prathamesh Kulkarni via Gcc-patches <gcc-patches@gcc.gnu.org> Reply-To: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org> X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1738325296097985045?= X-GMAIL-MSGID: =?utf-8?q?1738325296097985045?= |
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[aarch64] Use op_mode instead of vmode for op0, op1 in aarch64_vectorize_vec_perm_const
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Commit Message
Li, Pan2 via Gcc-patches
July 14, 2022, 10:55 a.m. UTC
Hi, For following test case: svint32_t foo() { int32x4_t v = (int32x4_t) { 1, 2, 3, 4 }; svint32_t v2 = svld1rq_s32 (svptrue_b8(), &v[0]); return v2; } After applying workaround in forwprop to not simplify VEC_PERM_EXPR in simplify_permutation to avoid type error in middle end (or using -fno-tree-forwprop) as mentioned in: https://gcc.gnu.org/pipermail/gcc-patches/2022-July/598390.html We get following optimized gimple: v2_2 = VEC_PERM_EXPR <{ 1, 2, 3, 4 }, { 1, 2, 3, 4 }, { 0, 1, 2, 3, ... }>; return v2_2; However we hit the following ICE during expansion of vec_perm_expr because in aarch64_vectorize_vec_perm_const, op0 is VECTOR_CST, and we call force_reg (VNx4SI, op0), which is incorrect mode for op0. The patch fixes it by using op_mode instead of vmode in calls to force_reg for op0 and op1. during RTL pass: expand foo2.c: In function ‘foo’: foo2.c:8:10: internal compiler error: in emit_move_insn, at expr.cc:4052 8 | return v2; | ^~ 0x74789b emit_move_insn(rtx_def*, rtx_def*) ../../gcc/gcc/expr.cc:4052 0xb8f664 force_reg(machine_mode, rtx_def*) ../../gcc/gcc/explow.cc:688 0x134182f aarch64_vectorize_vec_perm_const ../../gcc/gcc/config/aarch64/aarch64.cc:24132 0xe63070 expand_vec_perm_const(machine_mode, rtx_def*, rtx_def*, int_vector_builder<poly_int<2u, long> > const&, machine_mode, rtx_def*) ../../gcc/gcc/optabs.cc:6254 0xbb1569 expand_expr_real_2(separate_ops*, rtx_def*, machine_mode, expand_modifier) ../../gcc/gcc/expr.cc:10273 0xbb6498 expand_expr_real_1(tree_node*, rtx_def*, machine_mode, expand_modifier, rtx_def**, bool) ../../gcc/gcc/expr.cc:10625 0xa897dc expand_expr ../../gcc/gcc/expr.h:310 0xa897dc expand_return ../../gcc/gcc/cfgexpand.cc:3809 0xa897dc expand_gimple_stmt_1 ../../gcc/gcc/cfgexpand.cc:3918 0xa897dc expand_gimple_stmt ../../gcc/gcc/cfgexpand.cc:4044 0xa8f238 expand_gimple_basic_block ../../gcc/gcc/cfgexpand.cc:6096 0xa91187 execute ../../gcc/gcc/cfgexpand.cc:6822 Is the patch OK to commit after bootstrap+test on aarch64-linux-gnu ? Thanks, Prathamesh
Comments
Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> writes: > Hi, > For following test case: > > svint32_t foo() > { > int32x4_t v = (int32x4_t) { 1, 2, 3, 4 }; > svint32_t v2 = svld1rq_s32 (svptrue_b8(), &v[0]); > return v2; > } > > After applying workaround in forwprop to not simplify VEC_PERM_EXPR in > simplify_permutation to avoid type error in middle end (or using > -fno-tree-forwprop) > as mentioned in: > https://gcc.gnu.org/pipermail/gcc-patches/2022-July/598390.html > > We get following optimized gimple: > v2_2 = VEC_PERM_EXPR <{ 1, 2, 3, 4 }, { 1, 2, 3, 4 }, { 0, 1, 2, 3, ... }>; > return v2_2; Hmm, we really should be able to fold that to a constant. However… > However we hit the following ICE during expansion of vec_perm_expr > because in aarch64_vectorize_vec_perm_const, > op0 is VECTOR_CST, and we call force_reg (VNx4SI, op0), which is incorrect mode > for op0. The patch fixes it by using op_mode instead of vmode in calls > to force_reg > for op0 and op1. > > during RTL pass: expand > foo2.c: In function ‘foo’: > foo2.c:8:10: internal compiler error: in emit_move_insn, at expr.cc:4052 > 8 | return v2; > | ^~ > 0x74789b emit_move_insn(rtx_def*, rtx_def*) > ../../gcc/gcc/expr.cc:4052 > 0xb8f664 force_reg(machine_mode, rtx_def*) > ../../gcc/gcc/explow.cc:688 > 0x134182f aarch64_vectorize_vec_perm_const > ../../gcc/gcc/config/aarch64/aarch64.cc:24132 > 0xe63070 expand_vec_perm_const(machine_mode, rtx_def*, rtx_def*, > int_vector_builder<poly_int<2u, long> > const&, machine_mode, > rtx_def*) > ../../gcc/gcc/optabs.cc:6254 > 0xbb1569 expand_expr_real_2(separate_ops*, rtx_def*, machine_mode, > expand_modifier) > ../../gcc/gcc/expr.cc:10273 > 0xbb6498 expand_expr_real_1(tree_node*, rtx_def*, machine_mode, > expand_modifier, rtx_def**, bool) > ../../gcc/gcc/expr.cc:10625 > 0xa897dc expand_expr > ../../gcc/gcc/expr.h:310 > 0xa897dc expand_return > ../../gcc/gcc/cfgexpand.cc:3809 > 0xa897dc expand_gimple_stmt_1 > ../../gcc/gcc/cfgexpand.cc:3918 > 0xa897dc expand_gimple_stmt > ../../gcc/gcc/cfgexpand.cc:4044 > 0xa8f238 expand_gimple_basic_block > ../../gcc/gcc/cfgexpand.cc:6096 > 0xa91187 execute > ../../gcc/gcc/cfgexpand.cc:6822 > > Is the patch OK to commit after bootstrap+test on aarch64-linux-gnu ? > > Thanks, > Prathamesh > > diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc > index 25f4cbb466d..303814b8cca 100644 > --- a/gcc/config/aarch64/aarch64.cc > +++ b/gcc/config/aarch64/aarch64.cc > @@ -24129,11 +24129,11 @@ aarch64_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, > d.op_mode = op_mode; > d.op_vec_flags = aarch64_classify_vector_mode (d.op_mode); > d.target = target; > - d.op0 = op0 ? force_reg (vmode, op0) : NULL_RTX; > + d.op0 = op0 ? force_reg (op_mode, op0) : NULL_RTX; > if (op0 == op1) > d.op1 = d.op0; > else > - d.op1 = op1 ? force_reg (vmode, op1) : NULL_RTX; > + d.op1 = op1 ? force_reg (op_mode, op1) : NULL_RTX; > d.testing_p = !target; > > if (!d.testing_p) …yes, this is OK, thanks. Richard
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 25f4cbb466d..303814b8cca 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -24129,11 +24129,11 @@ aarch64_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, d.op_mode = op_mode; d.op_vec_flags = aarch64_classify_vector_mode (d.op_mode); d.target = target; - d.op0 = op0 ? force_reg (vmode, op0) : NULL_RTX; + d.op0 = op0 ? force_reg (op_mode, op0) : NULL_RTX; if (op0 == op1) d.op1 = d.op0; else - d.op1 = op1 ? force_reg (vmode, op1) : NULL_RTX; + d.op1 = op1 ? force_reg (op_mode, op1) : NULL_RTX; d.testing_p = !target; if (!d.testing_p)